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Principles of Operation
.
Prime Proprietary
number,
so the CPU passes the translated address from the STLB to the
memory address bus.
If the addresses do not match and the page is not found in memory
the
CPU
microcode generates a page fault to the operating system.
PRIMOS
accesses the paging device and reads
in
the
requested
page.
Then
PRIMOS
reexecutes
the
instruction
that caused the page fault.
The
STLB is updated, the address is found on the STLB, and the address
is
passed on the memory bus.
A
segment trap is generated if the STLB process ID does not match the
user ID.
The CPU microcode must access physical memory and update the
STLB.
This is because the translated physical
address
in
the
STLB
refers to another user's data.
4.2.7 CACHE MEMORY
Cache, located on the CPU B board (C on 750/850), is a small amount of
very
fast
memory which increases the effective speed of main memory.
In a Prime 750 system, access to cache memory
takes
80
nanoseconds.
Access to main memory takes 600 nanoseconds.
The system can do almost
eight
cache
accesses
in
the
time
it
takes to do one main memory
access.
Since programs tend to access the same memory locations over and over,
the system uses cache as an area to store data and instructions likely
to be used by the processor.
If the system can keep
everything
used
by a program in cache instead of main memory, the program will execute
much
more rapidly.
But because of the cost, cache memory is limited.
When a memory location is accessed, the contents are moved into
cache
in
a specific location determined by the virtual address word number.
Therefore, each access to that location in the future
will
find
the
information
in
cache, until the information is replaced by something
else,
As a further aid, information is always moved into cache in two
word pairs, so any access to the other word of the pair will
also
be
in cache.
Think of cache as a table of ordered pairs.
Each cache entry consists
of a physical page number (PPN), a piece of data and a validation bit.
Sequential
cache
locations
correspond
to
sequential physical word
locations, so the seventh cache entry for PPN 12 is the
seventh
word
on physical page 12.
4.2.7.1 CPU Cache Reads
All memory reads by the CPU are via cache.
When an instruction refers
to
a
memory location, the CPU microcode compares the virtual address
word number to the corresponding location in cache.
If the two
match
(cache
hit),
the
data
is passed from cache to the appropriate data
bus.
If the
two
do
not
match
(cache
miss),
the
CPU
microcode
generates
a
trap
which
causes
the
system to access the specified
location in main memory.
The CPU microcode loads the data
from
main
memory
into
the correct cache location.
Then the microcode restarts
the interrupted instruction.
Cache is accessed again and the
correct
data is output to the appropriate bus.
070-C
4-
10
eae
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