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Prime Proprietary
Operating Instructions
CP> MO RFABS
CP> D PPA
000014/000032: 000011 000115 /
CF> MO RPH
CP> A PPA
000014/000032: 000011 /
CP> MO RFL
CP> A PPA
000014/000032: 000115 /
CP>
3.6.1.9 Accessing CRS Register Files
Current Register Sets (CRS) are based on logical addresses
(see
"CRS
LOC
ADR"
column
in Table 3-7).
The CPU u-code converts the logical
address to the correct physical address, depending on Modals bits 9-11
(see Table 3-9).
Modals bit 9 is always 0 and bit 10 is always 1,
so
bit
11
actually
determines the CRS.
If Modals bit 11 is reset (0),
CRS is RF2.
If Modals bit 1] is set (1), CRS is RF3.
For example, if
PB (logical address '14) is accessed and Modals bit 11 is 0,
physical
address
'114 is displayed.
If PB is accessed and Modals bit 11 isl,
physical address '154 is displayed.
CP> MO RFCRS
CP> D KEYS :B
000014/000024: 1001100000100000
1100000001111111 /
CP> MO RFH
7
CP> A KEYS
000014/000024: 1001100000100000/
CP> MO RFL
7
CP> A KEYS
0000147000024: 1100000001111111/
CP>
3.6.1.10 Single-Stepping Instructions
"Single step" means executing a program in memory, one instruction
at
a
time.
Before starting, ensure that the proper Keys and Modals are
'set (see "Changing Processor Modes").
The registers and memory may be examined and modified
freely
between
singe-steps,
as
long
as
the
program
counter is not altered.
The
current. setting of
the
Keys
and
Modals
in
Current
Register
Set
location
24 will take affect each time a step is executed.
Interrupt
and DMX operations are disabled in single-step mode.
3.6.1.11 Changing Processor Modes
"SYSCLR" resets (to 0) the CPU Keys and Modals and puts the CPU in 16S
addressing mode.
The Current Register Set is
in
location
24.
The
high side of the register (KEYSH) contains the "Keys" and the low side
(KEYSL) contains the "Modals" (modes).
Each time the CPU executes the
fetch
cycle
of
a
new
instruction,
it
sets. its addressing modes
according to the Keys and Modals settings.
3
-
23
070-C
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