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General Description
PAVARCE Nunn} NNN
FIGURE 1-4:
;)
Prime Proprietary
La
ng
750/850 CPU SYSTEM (FCC)
cso-048
The more powerful 850 CPU, a multi-stream 1]-board processor, uses two
modified 750 processors under the control of a Stream
Synchronization
Unit
(SSU),
speed
processor has its own cache and IPU.
access
so
that cache is always current;
The 850
Stream Unit 1) controls I/O.
is increased 60 to 80 percent over the 750.
Each
The SSU manages physical
memory
the master CPU (Instruction
is
the
first
system
to
use
ultra-high
density
MOS
memory
chips with 64K x 1 bit dynamic RAMs.
Each memory board contains either
1/2Mb
or
1Mb_
storage.
supports a maximum of 128 users.
1.2 SPECIFICATIONS
General
and
physical
specifications
are
presented
through 1-4.
The
850
in
Tables 1-1
TABLE 1-1:
GENERAL SPECIFICATIONS: 150, 250-II, 550-II SYSTEMS
CENTRAL SYSTEM
150/250-II
550-II
Processor (number of boards)
2
3
Internal Data Paths
32 bit
32 bit
Instruction Pre~processor Unit
No
No
Multi-stream Achitecture
No
No
Error Correcting Memory
Yes
Yes
Interleaved Memory
Yes
Yes
Minimum Main Memory
. 25Mb(150-IT)
» 5Mb
« 5Mb(250-IT)
070-C
1-
Neer"
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