Timing And Control Unit. Ccccsccccccccesesensevcsscses; Arithmetic Unit; Memory Management. "200; Operating Modes - Prime Computer 50 Series Service Manual

Principles of Operation Prime Proprietary
s
BMSCSSXX L MEMORY
SLOT :
T — —
SELECT s CPU BOARD FUNCTIONS
E CONTROL ADDR.| DATA
L
XIS BOARD
/ 500 AND UP
M / ¢ DUAL PORT REG.FILE
I B J _—{ © DECIMAL ADDER (ALD)
Ss M / * BINARY ADDER—
c A 52-BiT (ALU)
7
HXXXXXX CPU B-BOARD
MISC y ¢ MASTER CLOCK
wise) PROCESSOR TOPHAT * INSTRUCTION DECODE PROM
¢ MICRO-CONTROL UNIT
© SEG. TABLE
LOOKASIDE BUFFER
(STLB)
3 3 \ ¢ MEMORY TIMER (PROM)
e p \ *¢ CACHE MEMORY
A D
\ CPU A-BOARD
T T NL | cpumicro-cove Prom
BPCINX lc | ¢ REGISTER FILES
p | 0 © CPU ADDER (ALU)
INTERRUPT A | ADDRESS [ N | n
&
NET) N_ | INSTRUCT. | A | A
DECODE
OMX T | roel
peconx NETL _ yy TO ALL SLOTS
CONTROLLERS
POWER SUPPLY
CS0-595
FIGURE 4-3: P550-II, 500, 650, SYSTEMS: CPU BLOCK DIAGRAM
Discussed in the next subsections is the following CPU information:
e Functional Description
e@ Timing and Control Unit
@ Arithmetic Unit
e@ Memory Management
@ Operating Modes
@ Segment Table Lookaside Buffer (STLB)
@ Cache Memory
@ Refresh
@ Processor Management
070-C 4- 4