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Principles of Operation
Prime Proprietary
Some controllers have more than one condition that may
be
tested
by
the
SKS.
When an SKS is executed on a controller, the function code
portion of the instruction determines the
specific
condition
to
be
tested.
4.2.11.1.3 Output Control Pulse (OCP)
The OCP differs from the other PIO instructions for two reasons:
e
ocP forces the controller's ready line true
e
OCP does not transfer any data to the controller.
The function code specifies some action to be taken by the controller.
The controller accepts the command, regardless of whether it
is
busy
or
not.
OCPs do not skip.
An OCP causes a specific operation to be
performed, such as initializing the controller or clearing a
specific
flip-flop.
4.2.11.2 Direct Memory Transfer (DMX)
Because
peripheral
controllers operate much slower than the CPU, PIO
is very inefficient.
If an OTA had to be issued
every
time
a
data
word
had
to be transferred to a peripheral, the CPU would spend most
of its time on I/O and never have
time
to
perform
other
important
operations,
such
as
running user programs.
To combat this problem,
hardware was designed to
automatically
transfer
data
to
and
from
peripheral controllers when the controller requests it.
The CPU sends
PIO
instructions
defining
the
operation
to
the
controller.
The
controller then takes control
of
the
operation.
This
process
is
called
a
"handshake".
The
CPU interrupts its normal operation and
performs the transfer.
Once the data transfer is
complete,
the
CPU
resumes
its
other tasks.
The entire process of interrupting the CPU
to perform a data transfer is called "Stealing a Cycle".
Another name for this data transfer process is DMX.
DMX implies
that
data
is
transferred directly from the peripheral to memory, but this
is not exactly true.
No controller has control over the
memory
bus.
As explained previously, normal CPU operation is momentarily suspended
so the CPU can perform the memory transfer.
There are five types of DMX:
@
Direct Memory Access (DMA)
@
Direct Memory Transfer (DMT)
@
Direct Memory Channel (DMC)
@
Direct Memory Queue (DMQ)
e@
Burst Mode Direct Memory Access (BDMA)
The steps in the DMX process are:
@®
'The controller sends control signalBPCDRO (DMX cycle
request)
to the CPU on the BPC.
070-C
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