Alinx Zynq UltraScale+MPSoC User Manual page 12

Fpga development board
Table of Contents

Advertisement

ACU19EG User Manual
PL_DDR4_DQS5_P
PL_DDR4_DQS6_N
PL_DDR4_DQS6_P
PL_DDR4_DQS7_N
PL_DDR4_DQS7_P
PL_DDR4_DQ0
PL_DDR4_DQ1
PL_DDR4_DQ2
PL_DDR4_DQ3
PL_DDR4_DQ4
PL_DDR4_DQ5
PL_DDR4_DQ6
PL_DDR4_DQ7
PL_DDR4_DQ8
PL_DDR4_DQ9
PL_DDR4_DQ10
PL_DDR4_DQ11
PL_DDR4_DQ12
PL_DDR4_DQ13
PL_DDR4_DQ14
PL_DDR4_DQ15
PL_DDR4_DQ16
PL_DDR4_DQ17
PL_DDR4_DQ18
PL_DDR4_DQ19
PL_DDR4_DQ20
PL_DDR4_DQ21
PL_DDR4_DQ22
PL_DDR4_DQ23
PL_DDR4_DQ24
PL_DDR4_DQ25
PL_DDR4_DQ26
PL_DDR4_DQ27
PL_DDR4_DQ28
PL_DDR4_DQ29
PL_DDR4_DQ30
www.alinx.com
IO_L4P_T0U_N6_DBC_AD7P_69
IO_L22N_T3U_N7_DBC_AD0N_69
IO_L22P_T3U_N6_DBC_AD0P_69
IO_L16N_T2U_N7_QBC_AD3N_69
IO_L16P_T2U_N6_QBC_AD3P_69
IO_L12N_T1U_N11_GC_70
IO_L9N_T1L_N5_AD12N_70
IO_L11P_T1U_N8_GC_70
IO_L8N_T1L_N3_AD5N_70
IO_L12P_T1U_N10_GC_70
IO_L8P_T1L_N2_AD5P_70
IO_L11N_T1U_N9_GC_70
IO_L9P_T1L_N4_AD12P_70
IO_L2P_T0L_N2_70
IO_L6P_T0U_N10_AD6P_70
IO_L2N_T0L_N3_70
IO_L6N_T0U_N11_AD6N_70
IO_L3P_T0L_N4_AD15P_70
IO_L5N_T0U_N9_AD14N_70
IO_L3N_T0L_N5_AD15N_70
IO_L5P_T0U_N8_AD14P_70
IO_L20N_T3L_N3_AD1N_70
IO_L24P_T3U_N10_70
IO_L21N_T3L_N5_AD8N_70
IO_L23N_T3U_N9_70
IO_L20P_T3L_N2_AD1P_70
IO_L21P_T3L_N4_AD8P_70
IO_L24N_T3U_N11_70
IO_L23P_T3U_N8_70
IO_L15P_T2L_N4_AD11P_70
IO_L14P_T2L_N2_GC_70
IO_L17P_T2U_N8_AD10P_70
IO_L14N_T2L_N3_GC_70
IO_L15N_T2L_N5_AD11N_70
IO_L18P_T2U_N10_AD2P_70
IO_L17N_T2U_N9_AD10N_70
G30
A40
A39
C34
D34
G25
J24
H25
J26
H24
K26
H26
J23
M25
M23
L25
L23
N24
N23
N25
P23
A28
A24
B27
C25
A27
C26
A25
C24
F27
F25
D27
E25
F28
F24
D28
12 / 36

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the Zynq UltraScale+MPSoC and is the answer not in the manual?

Questions and answers

This manual is also suitable for:

Acu19eg

Table of Contents