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2 EVM Setup and Features Explained
2.1 Evaluation Equipment
The following equipment can be used to evaluate the performance of the TIOL11xx and TIOS10xx devices.
•
A power supply capable of supplying 24 V across L+ (supply) and GND (ground)
•
A power supply capable of supplying 3.3 V or 5 V (if a TIOL11xx or TIOS10xx device without an internal LDO
is used)
•
An oscilloscope and probes capable of tolerating voltage as large as the L+ supply voltage
•
The logic interface pins (TX, EN, RX, NFAULT, and WAKE) can interface to a microcontroller, pattern
generator, or logic analyzer using 3.3-V or 5-V logic levels (to match the VCC_IN or VCC_OUT voltage).
•
If connecting to an IO-Link master node, an appropriate cable with either 3 or 4 wires for the L+, CQ, GND,
and optional DO signal can be connected to the 4-pin M12 connector, the wire terminal (J1), or test points.
•
External loading components such as resistors, inductors, capacitors, and so on. Can be connected to the
wire terminal (J1).
2.2 Power Overview
L+ is the primary supply voltage for the board and should be between 7-V and 36-V if the TIOL11xx device is
evaluated, but can be between 5-V and 36-V if only the TIOS10xx device is evaluated. The power supply should
be connected to pins 1 (L+) and 3 (GND) of the M12 connector (J2), pins 3 (L+) and 2 (GND) of the wire terminal
(J1), or test points TP11 (L+) and TP12 (GND).
The 3.3-V or 5-V digital logic voltage and board configuration may differ depending on which TIOL11xx and
TIOS10xx devices are installed. The EVM will support all versions of the TIOL11xx and TIOS10xx devices, both
with and without an LDO of either 3.3 V or 5 V. By default, a TIOL1123 and TIOS1023 will be installed and allow
each device to operate independently and supply its own logic level voltage derived from the single L+ power
supply. These devices are also compatible with the standard 3.3-V logic level of most TI microcontrollers that
may be used with this EVM.
If the board is configured with a version of the TIOL11xx and TIOS10XX that does not have an internal LDO,
such as the TIOL112 and TIOS102, then an external power supply will be needed for the logic level 3.3-V or 5-V.
An external power supply can be connected to pins 1 (VCC_EXT) and 2 (GND) of header J7 or to test points
TP20 (VCC_EXT) and TP10 (GND).
If a 3.3-V or 5-V voltage is supplied through pin 1 (3.3 V), pin 21 (5 V), and pin 22 (GND) of header J10, the
appropriate voltage can be used to supply the digital logic voltage to the board. Place a shunt on jumper J5
between pins 1 and 2 for the 3.3-V level, or pins 2 and 3 for the 5-V level. This will connect the voltage to pin
6 (VCC_LP) of the voltage connection header J9 and allow it to be used as the external supply voltage of the
board. It also allows connection to the power planes of the board supplying the device VCC_IN pins through a
shunt on pins 5 and 6 of header J9.
The VCC_IN and VCC_OUT pins of the TIOL11xx and TIOS10xx are connected to separate internal planes on
the board to allow any combination of devices to be configured and powered properly. The power plane net
for the TIOL11xx device (U1) is called VCC, and the power plane net for the TIOS10xx device (U2) is called
DO_VCC. Placing the shunt on pins 1 and 2 of header J9 will connect VCC, and a shunt placed on pins 3 and
4 will connect DO_VCC to the external supply voltage net. The LDO of either the TIOL11xx or TIOS10xx can be
used to supply the voltage for the board and other devices as well. The shunt locations on the connection header
J9 would remain the same, but the direction of current is different.
2.3 Current Limit Overview
The output current limit for the TIOL11xx and TIOS11xx devices can be configured through the ILIM_ADJ pins.
There is an external resistor on the ILIM_ADJ pin with a maximum settable current limit of 350 mA.
Connecting the ILIM_ADJ pin to GND increases the current limit to 500 mA for both the TIOL112x and TIOS102x
devices. This also allows the TIOL112x devices to enter a master mode, and allows it to source or sink a
minimum of 500 mA to generate a wake-up request. Also, while in this mode, the device enables a small current
sink of 5 mA (minimum) as required in the IO-Link standard specification, which calls for a minimum limit of 500
SLLU344 – FEBRUARY 2022
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EVM Setup and Features Explained
TIOx1x2x Evaluation Module
3
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