Table of Contents
Advertisement
EVM Setup and Features Explained
mA, it disables the current fault indication, as well as the Output Disable and Auto Recovery features of the
device.
Leaving the ILIM_ADJ pin floating sets the output current limit for the TIOL112x and TIOS102x devices to 300
mA, but disables the Output Disable and Auto Recovery if an over-current condition longer than the current fault
blanking time (t
) occurs. The NFAULT pin will still report this over-current fault condition, but the output will not
sc
be disabled and is useful when driving certain capacitive loads that may require a charging time greater than t
The EVM allows both the TIOL112x and TIOS102x ILIM_ADJ pins to be fully and independently configured
through headers J4 (TIOL112x) and J8 (TIOS102x). Placing a shunt on pins 3 and 4 of these headers connects
the device's ILIM_ADJ pin with a fixed resistor, that is by default 25.5 kΩ. Placing a shunt between pins 5 and
6 connects a variable resistance through the 100 kΩ potentiometers that can be adjusted to the desired current
limit for each device. Place a shunt between pins 1 and 2 to short the ILIM_ADJ pins to GND. Remove the shunt
from the headers completely to allow the ILIM_ADJ pins to float.
2.4 Fault Reporting (NFAULT)
The TIOL112x and TIOS102x can both monitor for three types of fault conditions and have a single fault
reporting pin (NFAULT) that is used to indicate that one or more of these faults are currently present in the
device. The NFAULT pin is driven low if either a current fault condition is detected, the die temperature has
exceeded the thermal warning threshold T(
(UVLO) threshold. NFAULT returns to a high-impedance state as soon as all three fault conditions clear.
The NFAULT signal for the TIOL112x (NFAULT) can be monitored through pin 19 of header J11, test point TP13,
and LED D1. Likewise, the NFAULT signal for the TIOS1012x (DO_NFAULT) can be monitored through pin 18 of
header J11, test point TP14, and LED D2.
2.5 Transient Protection and Custom Loads
The TIOx1x2x family of devices include on-chip ESD (IEC 61000-4-2) and surge (IEC 6100-4-5) protection,
which eliminates or reduces the size of any TVS diodes. Pads for external diodes (D3 – D7) are included on
the board, allowing the EVM to be modified to support the user's requirements. These pads can also be used
for other types of complex loads such as resistors, capacitors, and inductors that may be required during the
evaluation.
2.6 IO-Link Communication (TIOL112x)
The communication and control signals of the TIOL112x (TX, RX, EN, WAKE, and NFAULT) can be connected
to a microcontroller that is implementing an IO-Link protocol stack through pins 3 (RX), 4 (TX), 5 (EN), 8 (WAKE)
of header J10 as well as pin 19 (NFAULT) of header J11. Test points for each of these signals are also provided
next to the header pins, allowing the signals to be monitored or connected to additional test equipment, such as
oscilloscope probes and logic analyzers.
2.7 Digital Sensor Output Driver Control (TIOS102x and TIOS112x)
Both the TIOS102x and TIOL112x devices can be used in a push-pull, high-side, or low-side configuration to
drive resistive, large capacitive or large inductive loads.
The TIOS102x control signals can be connected to a microcontroller or test equipment through pins 11 (DO_IN),
17 (DO_EN), and 18 (DO_nFAULT) of header J11. Test points for each of these signals are also provided next
to the header pins, allowing the signals to be monitored or connected to additional test equipment, such as
oscilloscope probes and logic analyzers. The external load to be driven by the switch can be connected to the
wire terminal connector J1, M12 connector J2, or test points TP16 (DO), TP11 (L+_24V), and TP12 (GND).
The TIOL112x can operate as a digital sensor output driver similar to the TIOS102x. The control signals are the
same as the TIOS102x with the exception to the pin names where the TX pin is the Input, and the CQ is the
Output. These signals can be connected to a microcontroller or test equipment through pins 4 (TX) and 5 (EN)
of header J10 as well as pin 19 (NFAULT) of header J11. Test points for each of these signals are also provided
next to the header pins, allowing the signals to be monitored or connected to additional test equipment, such as
oscilloscope probes and logic analyzers. The external load to be driven by the switch can be connected to the
wire terminal connector J1, M12 connector J2, or test points TP15 (CQ), TP11 (L+_24V), and TP12 (GND).
4
TIOx1x2x Evaluation Module
), or supply has dropped below the under voltage lock out
WRN
Copyright © 2022 Texas Instruments Incorporated
www.ti.com
.
sc
SLLU344 – FEBRUARY 2022
Submit Document Feedback
Advertisement
Table of Contents
