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Versal AI Edge/Prime SOM Hardware User Guide iW-RainboW-G57M Versal AI Edge/Prime SOM Hardware User Guide Preliminary Information. Subject to change REL0.3 iWave Systems Technologies Pvt. Ltd. Page 1 of 63...
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(or authorized to receive for the recipient), you are hereby notified that any disclosure, copying distribution or use of any of the information contained within this document is STRICTLY PROHIBITED. Thank you. “iWave Systems Tech. Pvt. Ltd.”...
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No warranty of accuracy is given concerning the contents of the information contained in this publication. To the extent permitted by law no liability (including liability to any person by reason of negligence) will be accepted by iWave Systems, its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or inaccuracies in this document.
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3.2.3 Electrostatic Discharge ..........................58 Mechanical Characteristics ..........................59 3.3.1 Versal AI Edge SOM Mechanical Dimensions....................59 ORDERING INFORMATION ............................61 APPENDIX ................................62 Versal AI Edge SOM Development Platform ....................62 REL0.3 iWave Systems Technologies Pvt. Ltd. Page 5 of 63...
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Table 25: PS IOMUX on Versal AI Edge SOM ............................51 Table 26: Power Input Requirement ..............................55 Table 27: Power Sequence Timing ...............................56 Table 28: Temperature Specification ..............................58 Table 29: Orderable Product Part Numbers ............................61 REL0.3 iWave Systems Technologies Pvt. Ltd. Page 6 of 63...
Purpose This document is the Hardware User Guide for the Versal AI Edge/Prime System on Module. This board is fully supported by iWave Systems Technologies Pvt. Ltd. This Guide provides detailed information on the overall design and usage of the Versal AI Edge/ Prime System on Module from a Hardware Systems perspective.
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Secure Digital Input Output System On Chip Serial Peripheral Interface System On Module Transmitter UART Universal Asynchronous Receiver/Transmitter ULPI UTMI+ Low Pin Interface Universal Serial Bus USB OTG USB On The Go REL0.3 iWave Systems Technologies Pvt. Ltd. Page 8 of 63...
Note: Signal Type does not include internal pull-ups or pull-downs implemented by the chip vendors and only includes the pull-ups or pull-downs implemented On-SOM. References • Versal AI Edge/Prime Technical Reference Manual • Versal AI Edge/Prime Device Overview • Versal AI Edge/Prime AC and DC characteristics REL0.3 iWave Systems Technologies Pvt. Ltd. Page 9 of 63...
¹ Versal Prime doesn’t support AI/ML Engine ² GTYP transceiver is not supported in VE2102 & VE2002 Preliminary Information Subject to Change Figure 1: Versal AI Edge/Prime SOM Block Diagram REL0.3 iWave Systems Technologies Pvt. Ltd. Page 10 of 63...
12 LVDS/24 Single ended signals from XP Bank 702 • 27 LVDS/54 Single ended signals from XP Bank 703 • 20 Single ended signals from HD Bank 302 • Synchronous Clock In/Out • 10MHz Reference Clock Input REL0.3 iWave Systems Technologies Pvt. Ltd. Page 11 of 63...
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GTYP Transceiver’s are not supported in VE2002 & VE2102 devices. In Versal AI Edge/Prime SOM, PL XP & HD IO BANKs supports variable IO voltage setting which configurable through software. REL0.3 iWave Systems Technologies Pvt. Ltd. Page 12 of 63...
Figure 1: Versal AI Edge Simplified Block Diagram Note: Please refer the latest Versal AI Edge Datasheet & Technical Reference Manual for more details which may be revised from time to time. REL0.3 iWave Systems Technologies Pvt. Ltd. Page 13 of 63...
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PS, there is option in Versal to route IO peripheral interfaces to PL Bank I/O pins referred as EMIO (Extended MIO). Versal AI Edge PS Peripheral Pin mapping options between MIO & EMIO is shown below. REL0.3 iWave Systems Technologies Pvt. Ltd. Page 14 of 63...
Also, Versal AI Edge supports 8 high-speed transceiver GTYP from Programmable Logic (PL). These transceivers are arranged in groups of four known as a transceiver Quad with Bank 103 & Bank 104 and supported line rate of 32 Gb/s. REL0.3 iWave Systems Technologies Pvt. Ltd. Page 15 of 63...
MIO or high-density I/O (HDIO) pins can be used by the SYSMON for measuring voltage levels external to the device. REL0.3 iWave Systems Technologies Pvt. Ltd. Page 16 of 63...
DONE_503 is output and its in open drain pin with weak internal pullup. This pin will become high when the boot sequence is complete. By default this pin is connected to VCC_1V8 through 4.7K. REL0.3 iWave Systems Technologies Pvt. Ltd. Page 17 of 63...
PS JTAG QSPI Note: SW4 boot media switch is assembled in the Carrier board to control SOM Boot media and SOM boot mode signals are connected to SW4 through Board-to-Board connector2. REL0.3 iWave Systems Technologies Pvt. Ltd. Page 18 of 63...
PMIC’s Buck and LDO regulator is used for on SOM peripherals. Also, PMIC supports reset output and connected to Versal AI Edge (POR_B_503) for power on reset. Important Note: Every Power Off and On, The DA9062 PMIC work as initial OTP Setting REL0.3 iWave Systems Technologies Pvt. Ltd. Page 20 of 63...
SD0 controller of the Versal’s PS through MIO pins and operates at 1.8V Voltage level. This SD/SDIO controller supports eMMC 5.1 standard with up to 8bit HS400 mode. The eMMC Flash size can be expandable based on the availability of higher density eMMC Flash device. REL0.3 iWave Systems Technologies Pvt. Ltd. Page 21 of 63...
Figure 3: Fan Header Table 6: Fan Header Pinout Versal Versal Versal Signal Type/ Pin No Signal Name Description Pin Name Bank Pin No Termination VCC_5V O, 5V Power Supply Voltage. Power Ground. REL0.3 iWave Systems Technologies Pvt. Ltd. Page 22 of 63...
SOM as shown below. Number of Pins - 240 Connector Part Number - ADM6-60-01.5-L-4-2-A-TR from Samtech Mating Connector - ADF6-60-03.5-L-4-2-A-TR from Samtech Staking Height - 5mm Figure 4: Board to Board Connector 1 REL0.3 iWave Systems Technologies Pvt. Ltd. Page 23 of 63...
Clock input. IO, 1.5V XP Bank703 IO21 differential XP_B20_LVDS703_L21 IO_L21P_XCC_N7P0 positive or single ended I/O. _703 XP_C21_LVDS703_L21 IO_L21N_XCC_N7P1 IO, 1.5V XP Bank703 IO21 differential _703 negative or single ended I/O. REL0.3 iWave Systems Technologies Pvt. Ltd. Page 26 of 63...
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I/O. _703 XP_C27_LVDS703_L5P IO_L5P_N1P4_703 IO, 1.5V XP Bank703 IO5 differential positive or single ended I/O. XP_B28_LVDS703_L5N IO_L5N_N1P5_703 IO, 1.5V XP Bank703 IO5 differential negative or single ended I/O. REL0.3 iWave Systems Technologies Pvt. Ltd. Page 27 of 63...
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IO_L20N_N6P5_703 negative or single ended I/O. XP_H23_LVDS703_L12 IO_L12P_GC_XCC_N IO, 1.5V XP Bank703 IO12 differential P_GC 4P0_703 positive or single ended I/O. Same pin can be used as Global Clock input. REL0.3 iWave Systems Technologies Pvt. Ltd. Page 28 of 63...
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I/O. *IO Type of IOs originating from Versal AI Edge SoC is configurable. Hence for exact IO type configuration options, refer Xilinx Versal AI Edge datasheet. REL0.3 iWave Systems Technologies Pvt. Ltd. Page 29 of 63...
I/O. XP_R22_LVDS702_L19N IO_L19N_N6P3_M0P IO, 1.5V XP Bank702 IO19 differential 147_702 negative or single ended I/O. XP_R21_LVDS702_L20P IO_L20P_N6P4_M0P IO, 1.5V XP Bank702 IO20 differential positive or single ended I/O. 148_702 REL0.3 iWave Systems Technologies Pvt. Ltd. Page 30 of 63...
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I/O _M0P139_702 XP_L23_LVDS702_L16P IO_L16P_N5P2_M0P IO, 1.5V XP Bank702 IO16 differential 140_702 positive or single ended I/O. XP_K24_LVDS702_L16N IO_L16N_N5P3_M0P IO, 1.5V XP Bank702 IO16 differential 141_702 negative or single ended I/O REL0.3 iWave Systems Technologies Pvt. Ltd. Page 31 of 63...
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I/O. *IO Type of IOs originating from Versal AI Edge SoC is configurable. Hence for exact IO type configuration options, refer Xilinx Versal AI Edge datasheet. REL0.3 iWave Systems Technologies Pvt. Ltd. Page 32 of 63...
HD_C14_SE302_L1P IO_L1P_302 IO, 1.8V HD Bank302 IO1 single ended I/O. HD_C13_SE302_L1N IO_L1N_302 IO, 1.8V HD Bank302 IO1 single ended I/O. IO, 1.8V HD Bank302 IO2 single ended I/O. HD_E13_SE302_L2P IO_L2P_302 REL0.3 iWave Systems Technologies Pvt. Ltd. Page 33 of 63...
SOM as shown below. Number of Pins - 240 Connector Part Number - ADM6-60-01.5-L-4-2-A-TR from Samtech Mating Connector - ADF6-60-03.5-L-4-2-A-TR from Samtech Staking Height - 5mm Figure 5: Board to Board Connector 2 REL0.3 iWave Systems Technologies Pvt. Ltd. Page 35 of 63...
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Versal AI Edge SOM Hardware User Guide B2B-2 Signal Name B2B- Signal Name B2B-2 Pin Signal Name B2B-2 Signal Name 2 Pin *Power rails are highlighted in RED and Clock signals are highlighted in purple. REL0.3 iWave Systems Technologies Pvt. Ltd. Page 38 of 63...
USB OTG ID input for USB host or USB_OTG_ID device detection. O, 3.3V USB active high power enable output USB_PWR_EN CMOS to control external USB Vbus. VBUS_USB I, 5V Power USB VBUS for VBUS monitoring. REL0.3 iWave Systems Technologies Pvt. Ltd. Page 39 of 63...
IO, GBE Gigabit Ethernet differential pair 4 GPHY_DTXRXM negative. O, GBE Gigabit Ethernet Activity LED (Active GPHY_ACTIVITY_LED1 High). O, GBE Gigabit Ethernet 1000Mbps Link GPHY_LINK_LED2 status LED (Active High). REL0.3 iWave Systems Technologies Pvt. Ltd. Page 40 of 63...
Pin No Signal Name Bank Termination I2C_SCL(PMC_MIO5 PMC_MIO50_501 AB10 O, 1.8V OD/ I2C Serial Clock. 0_501) 4.7K PU I2C_SDA(PMC_MIO PMC_MIO51_501 AA10 IO, 1.8V OD/ I2C Serial Data. 51_501) 4.7K PU REL0.3 iWave Systems Technologies Pvt. Ltd. Page 43 of 63...
JTAG_TDI TDI_503 AG10 I, 1.8V LVCMOS/ JTAG Test Data Input. 4.7K JTAG_TDO TDO_503 O, 1.8V LVCMOS JTAG Test Data Output. JTAG_TMS TMS_503 I, 1.8V LVCMOS/ JTAG Test Mode Select. 4.7K REL0.3 iWave Systems Technologies Pvt. Ltd. Page 45 of 63...
The Versal AI Edge SOM support an optional reference clock 1 input for GTYP Bank 103 & 104 from board-to-board connector 2 with a pins of C31, C32, D31, D42. For more details on Power pins on Board-to-Board Connector2, refer the below table. REL0.3 iWave Systems Technologies Pvt. Ltd. Page 48 of 63...
Optional Reference clock1 for K1P_104 KP1_104 GTYP Bank 104 B2B_GTYP_REFCL GTYP_REFCL I, DIFF Optional Reference clock1 for K1N_104 KN1_104 GTYP Bank 104 VRTC_3V0 I, 3V Power 3V backup coin cell input for RTC. REL0.3 iWave Systems Technologies Pvt. Ltd. Page 49 of 63...
²Versal AI Edge SOM uses this voltage as backup power source to PMIC RTC when VCC_5V is off. This is an optional power and required only if RTC functionality is used. REL0.3 iWave Systems Technologies Pvt. Ltd. Page 55 of 63...
SOMPWR_EN fall time to VCC_5V fall time ≥ 0 ms VCC_5V fall time to VRTC_3V0 fall time ≥ 0 ms ¹ VRTC_3V0 is the RTC Battery backup supply. This is an optional power. REL0.3 iWave Systems Technologies Pvt. Ltd. Page 56 of 63...
3.2.3 Electrostatic Discharge iWave’s Versal AI Edge SOM is sensitive to electro static discharge and so high voltages caused by static electricity could damage some of the devices on board. It is packed with necessary protection while shipping. Do not open or use the SOM except at an electrostatic free workstation.
Versal AI Edge SOM PCB size is 50mm x 60mm x 1.83mm. SOM mechanical dimension is shown below. Figure 7: Mechanical dimension of Versal AI Edge SOM SOM - Top View REL0.3 iWave Systems Technologies Pvt. Ltd. Page 59 of 63...
3.5mm and bottom side maximum height component is Board to Board connector 1 & 2 (4.1mm). Please refer the below figure which gives height details of Versal SOM. Figure 9: Top and Bottom Maximum Heighted Component REL0.3 iWave Systems Technologies Pvt. Ltd. Page 60 of 63...
The below table provides the standard orderable part numbers for different Versal AI Edge SOM variations. Please contact iWave for orderable part number of higher RAM memory size or Flash memory size SOM configurations. Also, if the desired part number is not listed in below table or if any custom configuration part number is required, please contact iWave.
Versal AI Edge SOM Development Platform iWave Systems supports iW-RainboW-G57M– Versal AI Edge SOM Development Platform which is targeted for quick validation of Versal based SOM. iWave's Versal AI Edge Development Board incorporates Versal AI Edge SOM and High-performance Carrier board with complete BSP support.
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