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General Description
1 .1 1 OT H E R S T ANDAR D F E AT U R E S
• 1- to 3-Phase Programmable
• IEEE 488.2 Interface
• SCPI Protocol
• Waveform Trigger Output
(1 MegΩ Load Drive; positive edge is at 0 ±30 µs, 0 to 5V logic)
• SYNC OUT. User programmed for:
Cycle Start, all cycles
For loads ≥2 kΩ: Vout ≤1V Low State; Vout ≥2.4V High State;
Negative edge is at 0 ±30 µs.
• CLOCK/LOCK
CLOCK pulses at programmed frequency for loads ≥2 kΩ Vout ≤1V Low State;
Vout ≥2.4V High State. Negative edge is at 0 ±30 µs.
LOCK locks output to input 'TTL' frequency; signal needs to supply
pull down current of 15 mA with voltage drop of ≤0.6V; no pull up needed.
Negative edge is at 0 ±30 µs.
• LOCK Specifications
Frequency range is 40.00 Hz to 500.00 Hz.
Tracking range is ±10% of programmed center frequency.
Duty cycle is 50% ±10%.
Slew rate is .02% of input frequency/second, maximum, which produces a maximum
phase shift of 5 from the lock input falling edge to the output rising edge.
The rising edge of the output will be locked to the falling edge of the lock input and
will have less than a 30 µsec propagation delay.
Maximum output jitter when locked is <1% of lock input period.
PLL lock is achieved in <5 seconds.
• External Amplitude Modulation
0 to 5 VRMS provides 0 to ≥20% output amplitude modulation
(±2% of full scale output).
1-8
TW 3700 • TW 5550
Elgar TrueWave
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