Solder Bridges; Table 6. Solder Bridges - ST STM32F3DISCOVERY User Manual

Hardware layout and configuration
6.11

Solder bridges

Bridge
SB17,18
(2)
(X1 crystal)
SB1,3,5,8 (default)
SB2,4,6,9 (reserved)
SB14,16
(X3 crystal)
SB23
(B2-RESET)
SB20
(B1-USER)
SB13,15
(RX, TX)
SB7
(NRST)
SB10
(SWO)
SB11
(STM_RST)
SB19
(BOOT0)
SB21,22
(USB USER)
SB12
(2)
(MCO)
1. The default state is shown in bold.
2. If SB12 is ON, SB17 and R33 must be OFF to provide the clock source from the MCO correctly.
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Table 6. Solder bridges

(1)
State
X1, C22, C23, R32, and R33 provide a clock. PF0 and PF1 are disconnected from
OFF
P2.
ON PF0 and PF1 are connected to P2 (R32 and R33 must be OFF).
ON Reserved, do not modify
OFF Reserved, do not modify
X3, C14, C26, R29, and R30 deliver a 32 KHz clock. PC14 and PC15 are not
OFF
connected to P2.
ON PC14 and PC15 are only connected to P2. R29 and R30 are OFF.
ON B2 push-button is connected to NRST of STM32F303VCT6
OFF B2 push-button is not connected to NRST of STM32F303VCT6
ON B1 push-button is connected to PA0
OFF B1 push-button is not connected to PA0
STM32F303VCT6 USART1 is not connected to ST-LINK, so VCP is disabled
OFF
(Default configuration on PCB version A or B).
STM32F303VCT6 USART1 is connected to ST-LINK, so VCP is enabled (default
ON
configuration on PCB version C and newer).
ON NRST signal of CN3 is connected to NRST of STM32F303VCT6
OFF NRST signal is not connected
ON SWO signal of CN3 is connected to PB3
OFF SWO signal is not connected
OFF No incidence on NRST signal of STM32F103C8T6
ON NRST signal of STM32F103C8T6 is connected to GND
ON BOOT0 signal of STM32F303VCT6 is at level LOW through 510 Ω pull-down
BOOT0 signal of STM32F303VCT6 is at level HIGH through 10 K Ω pull-up (not
OFF
provided).
PA11 and PA12 are only used for USB USER and not connected to P2 to avoid
OFF
noise.
ON PA11 and PA12 are connected to P2.
OFF The MCO signal of STM32F103C8T6 is not used.
MCO clock signal from STM32F103C8T6 is connected to OSC_IN of
ON
STM32F303VCT6.
Description
UM1570 Rev 7
UM1570