Texas Instruments ADS1263EVM-PDK User Manual page 31

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Remove shunt to apply
external LDO source to JP-2
JP2
TP4
EVM_REG_5V5
R38
C26 100k
10uF
R29
10.0k
GND
R32 0
D1
Green
R35 0
GND
GND
GND
EVM/PHI Power
5V_LDO AVDD
Remove shunt to apply
external AVDD source to
JP3-2
JP3
Power Indicators
AVDD
R28
6.65k
D2
Green
GND
SBAU206B – APRIL 2015 – REVISED MAY 2023
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5.5V -> 5V Analog LDO
U3 5V_LDO
15 1
IN OUT
16 20
IN OUT
13 3
EN SENSE/FB
12
0P1V
11
0P2V
10
0P4V
9
0P8V
8 2
1P6V NC
6 17
3P2V NC
5 18
6P4V1 NC
4 19
6P4V2 NC
GND
7
GND
14 21
NR Thermal_Pad
TPS7A4700RGWR
C27
1uF
GND
3.3V_EVM DVDD
DVDD
TP9
To apply external DVDD
remove shunt apply to
JP1-2
JP1
DVDD
R30
6.65k
D3
Green
GND
Figure 8-3. ADS1263EVM Power, Clock, and Voltage Reference Circuits
Copyright © 2023 Texas Instruments Incorporated
External Reference (OPTIONAL)
TP5
AVDD U4
2
VIN
R39
0.1 C29
DNP
2.2uF
C28
22µF 1
EN
REF7025QDGKR
GND
Ground Tree
GND
TP11
External Clock (Optional)
DVDD
Y1
4
VDD
C25
DNP 1
STANDBY
0.1uF
ASEMB-7.3728MHZ-XY-T
GND
Clock has a VDD max of
3.3V --> disconnect DVDD
shunt to apply
J7
1
DNP
EXT Clock
GND
Bill of Materials, PCB Layout, and Schematics
7 R42
OUTF DNP
6
OUTS
C30
DNP
22uF
DNP
3
GND
R41
4
GND DNP
0.01
5
GND
8 R43
GND DNP
GND
GND GND GND
TP12 TP13 TP1
GND
3 R31 0
OUT DNP
DNP
2
GND
GND
GND
R37 0
DNP
ADS1263EVM-PDK Evaluation Module
TP7
0 REFP
REFP
TP8
0 REFN
REFN
CLKIN
R44
0
31