Analog Devices MAX77859 Manual page 12

MAX77859 Evaluation Kit
Figure 14. Configuration Tab—Miscellaneous Configuration Sections
Layout Guideline
Careful circuit board layout is critical to achieving low switching power losses and clean, stable operation. The EV kit
serves as a recommended layout for the MAX77859. A high-density interconnect (HDI) PCB is required to route to the
EN, FPWM, SEL, and SRP pins.
layout files for guidance when designing with the IC. The IC data sheet contains a list of useful tips and guidelines for
achieving the best possible layout. They are repeated here for convenience:
•
Place the input capacitors (C
respectively. Since the IC operates at a high switching frequency, this placement is critical for minimizing parasitic
inductance within the input and output current loops, which can cause high voltage spikes and can damage the internal
switching MOSFETs.
•
Place the inductor next to the LX bumps (as close as possible) and make the traces between the LX bumps and the
inductor short and wide to minimize PCB trace impedance. Excessive PCB impedance reduces converter efficiency.
When routing LX traces on a separate layer (as in the example), make sure to include enough vias to minimize trace
impedance. Routing LX traces on multiple layers is recommended to further reduce trace impedance. Furthermore,
do not let LX traces take up an excessive amount of area. The voltage on this node switches very quickly and an
additional area creates more radiated emissions.
•
Route LX nodes to their corresponding bootstrap capacitor (C
reduce trace length to the IC.
•
Connect the inner PGND bumps to the low-impedance ground plane on the PCB with vias placed next to the bumps.
Do not create PGND islands, as PGND islands risk interrupting the hot loops. Connect AGND and AGND island to the
low-impedance ground plane on the PCB (the same net as PGND).
•
Keep the power traces and load connections short and wide. This is essential for high converter efficiency.
•
When utilizing the output current sense feature (MAX77859A only), route SRP and SRN to the sense resistor in
parallel, and make sure the traces are as short as possible to limit the amount of noise couple in the signal.
•
Do not neglect ceramic capacitor DC voltage derating. Choose capacitor values and case sizes carefully. Refer to the
Output Capacitor Selection section in the MAX77859 IC data sheet and
www.analog.com
Figure 15 shows an example layout for the MAX77859 WLP package. Use the provided
) and output capacitors (C
IN
Evaluates: MAX77859 (WLP)
) immediately next to the IN pin and OUT pin of the IC,
OUT
) as short as possible. Prioritize C
BST
Tutorial 5527
placement to
BST
for more information.
Analog Devices | 12