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A.2
Counter operating modes
A.2.1
MODE 0 – Stop on terminal count
The output will be initially low after you set this mode of operation. After you load the
count into the selected count register, the output will remain low and the counter will
count. When the counter reaches the terminal count, its output will go high and
remain high until you reload it with the mode or a new count value. The counter con-
tinues to decrement after it reaches the terminal count. Rewriting a counter register
during counting has the following results:
1.
Writing to the first byte stops the current counting.
2.
Writing to the second byte starts the new count.
A.2.2
MODE 1 – Programmable one-shot
The output is initially high. The output will go low on the count following the rising
edge of the gate input. It will then go high on the terminal count. If you load a new
count value while the output is low, the new value will not affect the duration of the
one-shot pulse until the succeeding trigger. You can read the current count at any
time without affecting the one-shot pulse. The one-shot is retriggerable, thus the out-
put will remain low for the full count after any rising edge at the gate input.
A.2.3
MODE 2 – Rate generator
The output will be low for one period of the input clock. The period from one output
pulse to the next equals the number of input counts in the counter register. If you
reload the counter register between output pulses, the present period will not be
affected, but the subsequent period will reflect the value.
The gate input, when low, will force the output high. When the gate input goes high,
the counter will start from the initial count. You can thus use the gate input to synchro-
nize the counter.
With this mode the output will remain high until you load the count register. You can
also synchronize the output by software.
A.2.4
MODE 3 – Square wave generator
This mode is similar to Mode 2, except that the output will remain high until one half
of the count has been completed (for even numbers), and will go low for the other half
of the count. This is accomplished by decreasing the counter by two on the falling
edge of each clock pulse. When the counter reaches the terminal count, the state of
the output is changed, the counter is reloaded with the full count and the whole pro-
cess is repeated.
If the count is odd and the output is high, the first clock pulse (after the count is
loaded) decrements the count by 1. Subsequent clock pulses decrement the count by
2. After time out, the output goes low and the full count is reloaded. The first clock
pulse (following the reload) decrements the counter by 3. Subsequent clock pulses
decrement the count by two until time out, then the whole process is repeated. In this
way, if the count is odd, the output will be high for (N+1)/2 counts and low for (N-1)/2
counts.
PCI-1750/PCI-1750SO User Manual
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