The Intel 8254; Counter Read/Write And Control Registers - Advantech PCI-1750SO User Manual

A.1

The Intel 8254

The PCI-1750/PCI-1750SO uses one Intel 8254 compatible programmable interval
timer/counter chip. The popular 8254 offers three independent 16-bit down counters.
Each counter has a clock input, control gate and an output. You can program each
counter for maximum count values from 2 to 65535.
The 8254 has a maximum input clock frequency of 10 MHz. The PCI-1750/PCI-
1750SO provides 10 MHz input frequencies to the counter chip from an on-board
crystal oscillator.
On the PCI-1750/PCI-1750SO, the 8254 chip's Timer 0 and Timer 1 are cascaded to
be a 32-bit programmable timer.
A.1.1

Counter read/write and control registers

The 8254 programmable interval timer uses four registers at addresses BASE +
24(Dec), BASE + 25(Dec), BASE + 26(Dec) and BASE + 27(Dec) for read, write and
control of counter functions.
Register functions appear below:
Register
BASE + 24(Dec)
BASE + 25(Dec)
BASE + 26(Dec)
BASE + 27(Dec)
Since the 8254 counter uses a 16-bit structure, each section of read/write data is split
into a least significant byte (LSB) and most significant byte (MSB). To avoid errors it
is important that you make read/write operations in pairs and keep track of the byte
order.
The data format for the control register appears below:
BASE+27(Dec) 8254 control, standard mode
Bit D7
Value SC1
A.1.1.1 Description
SC1 & SC0 Select counter
Counter
0
1
2
Read-back command
RW1 & RW0 Select Read/Write Operation
Operation
Counter Latch
Read/Write LSB
Read/Write MSB
Read/Write LSB first then MSB
PCI-1750/PCI-1750SO User Manual
Function
Counter 0 read/write
Counter 1 read/write
Counter 2 read/write
Counter control word
D6 D5 D4 D3
SC0 RW1 RW0 M2
SC1 SC0
0 0
0 1
1 0
1 1
RW1 RW0
0 0
0 1
1 0
1 1
24
D2 D1 D0
M1 M0 BCD