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Manuals and User Guides for Texas Instruments PCI7421. We have
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Texas Instruments PCI7421 manual available for free PDF download: Data Manual
Texas Instruments PCI7421 Data Manual (299 pages)
dual/single socket cardbus and ultramedia controller with integrated 1394a-2000 ohci two-port phy/link-layer controller with dedicated flash media socket
Brand:
Texas Instruments
| Category:
Controller
| Size: 1 MB
Table of Contents
Table of Contents
3
Section Title Page
9
Table Title Page
14
Cardbus Socket Registers
15
Introduction
19
Controller Functional Description
19
PCI7621 Controller
19
PCI7421 Controller
20
PCI7611 Controller
20
Multifunctional Terminals
21
PCI Bus Power Management
21
PCI7411 Controller
21
Power Switch Interface
21
Features
22
Related Documents
23
Trademarks
24
Terms and Definitions
25
Ordering Information
25
Terminal Descriptions
27
PCI7621 GHK/ZHK-Package Terminal Diagram
27
PCI7421 GHK/ZHK-Package Terminal Diagram
28
PCI7611 GHK/ZHK-Package Terminal Diagram
29
PCI7411 GHK/ZHK-Package Terminal Diagram
30
Signal Names by GHK Terminal Number
31
Cardbus PC Card Signal Names Sorted Alphabetically
35
Bit PC Card Signal Names Sorted Alphabetically
37
Detailed Terminal Descriptions
39
Power Supply Terminals
40
PC Card Power Switch Terminals
41
PCI System Terminals
41
PCI Address and Data Terminals
42
PCI Interface Control Terminals
43
Multifunction and Miscellaneous Terminals
44
Bit PC Card Address and Data Terminals
45
Bit PC Card Interface Control Terminals
46
Cardbus PC Card Interface System Terminals
48
Cardbus PC Card Address and Data Terminals
49
Cardbus PC Card Interface Control Terminals
50
IEEE 1394 Physical Layer Terminals
52
Memory Stick/Pro Terminals
53
SD/MMC Terminals
53
Smart Media/XD Terminals
54
Smart Card Terminals
55
Feature/Protocol Descriptions
57
Power Supply Sequencing
57
Pci7X21/Pci7X11 System Block Diagram
57
1394 PCI Bus Master
58
Clamping Voltages
58
I/O Characteristics
58
Peripheral Component Interconnect (PCI) Interface
58
State Bidirectional Buffer
58
PCI Bus Support
58
Device Resets
59
Serial EEPROM I 2 C Bus
59
PCI Reset Requirement
59
Functions 0 and 1 (Cardbus) Subsystem Identification
60
Serial ROM Application
60
Function 2 (OHCI 1394) Subsystem Identification
61
Function 3 (Flash Media) Subsystem Identification
61
Function 4 (SD Host) Subsystem Identification
61
Function 5 (Smart Card) Subsystem Identification
61
PC Card Applications
61
Low Voltage Cardbus Card Detection
62
PC Card Insertion/Removal and Recognition
62
Ultramedia Card Detection
62
Flash Media Card Detection
63
PC Card-Card Detect and Voltage Sense Connections
63
Internal Ring Oscillator
64
Power Switch Interface
64
TPS2228 Control Logic-Xvpp/Vcore
64
TPS2228 Control Logic-XVCC
64
TPS2226 Control Logic-Xvpp
64
TPS2226 Control Logic-XVCC
64
Integrated Pullup Resistors for PC Card Interface
65
LED Socket Activity Indicators
65
SPKROUT and CAUDPWM Usage
65
SPKROUT Connection to Speaker Driver
65
Cardbus Socket Registers
66
Mhz Clock Requirements
66
Two Sample LED Circuits
66
Accessing Serial-Bus Devices through Software
67
Serial EEPROM Interface
67
Serial-Bus Interface Implementation
67
Serial-Bus Interface Protocol
67
Pci7X21/Pci7X11 Registers Used to Program Serial-Bus Devices
67
Serial-Bus Start/Stop Conditions and Bit Transfers
68
Serial-Bus Protocol Acknowledge
68
Serial-Bus Protocol—Byte Write
68
Serial-Bus EEPROM Application
69
Serial-Bus Protocol—Byte Read
69
EEPROM Interface Doubleword Data Collection
69
EEPROM Loading Map
70
Programmable Interrupt Subsystem
72
Interrupt Mask and Flag Registers
73
PC Card Functional and Card Status Change Interrupts
73
Interrupt Masks and Flags
74
PC Card Interrupt Events and Description
74
IRQ Implementation
75
Using Parallel IRQ Interrupts
75
Using Parallel PCI Interrupts
75
Power Management Overview
76
SMI Support in the Pci7X21/Pci7X11 Controller
76
Using Serialized IRQSER Interrupts
76
Interrupt Pin Register Cross Reference
76
SMI Control
76
Power Management (Function 2)
77
System Diagram Implementing Cardbus Device Class Power Management
77
Cardbus (Functions 0 and 1) Clock Run Protocol
78
Cardbus PC Card Power Management
78
Integrated Low-Dropout Voltage Regulator (LDO-VR)
78
Requirements for Internal/External 1.5-V Core Power Supply
78
Bit PC Card Power Management
79
Requirements for Suspend Mode
79
Signal Diagram of Suspend Function
79
Suspend Mode
79
Ring Indicate
80
RI_OUT Functional Diagram
80
PCI Power Management
81
Power-Management Registers
81
Cardbus Bridge Power Management
82
Flash Media (Function 3 Power Management
82
Function 2 Power-Management Registers
82
Function 3 Power-Management Registers
82
Function 4 Power-Management Registers
82
Function 5 Power-Management Registers
82
OHCI 1394 (Function 2 Power Management
82
SD Host (Function 4 Power Management
82
Smart Card (Function 5 Power Management
82
ACPI Support
83
Block Diagram of a Status/Enable Cell
83
Master List of PME Context Bits and Global Reset-Only Bits
83
IEEE 1394 Application Information
86
PHY Port Cable Connection
86
TP Cable Connections
86
Typical Compliant DC Isolated Outer Shield Termination
86
Crystal Selection
87
Non-DC Isolated Outer Shield Termination
87
Bus Reset
88
Load Capacitance for the Pci7X21/Pci7X11 PHY
88
Recommended Crystal and Capacitor Layout
88
PC Card Controller Programming Model
91
PCI Configuration Register Map (Functions 0 and 1)
91
Bit Field Access Tag Descriptions
91
Functions 0 and 1 PCI Configuration Register Map
91
Vendor ID Register
92
Device ID Register Functions 0 and 1
93
Command Register
94
Command Register Description
94
Status Register
95
Status Register Description
95
Cache Line Size Register
96
Class Code Register
96
Revision ID Register
96
BIST Register
97
Header Type Register
97
Latency Timer Register
97
Capability Pointer Register
98
Cardbus Socket Registers/Exca Base Address Register
98
Secondary Status Register
99
Secondary Status Register Description
99
Cardbus Bus Number Register
100
PCI Bus Number Register
100
Subordinate Bus Number Register
100
Cardbus Latency Timer Register
101
Cardbus Memory Base Registers 0, 1
101
Cardbus I/O Base Registers 0, 1
102
Cardbus Memory Limit Registers 0, 1
102
Cardbus I/O Limit Registers 0, 1
103
Interrupt Line Register
103
Interrupt Pin Register
104
Bridge Control Register
105
Interrupt Pin Register Cross Reference
105
Type
105
Bridge Control Register Description
105
Subsystem Vendor ID Register
106
PC Card 16-Bit I/F Legacy-Mode Base-Address Register
107
Subsystem ID Register
107
System Control Register
108
System Control Register Description
108
MC_CD Debounce Register
110
Rw Rw Rw Rw
110
General Control Register
111
General Control Register Description
112
General-Purpose Event Status Register
113
General-Purpose Event Status Register Description
113
General-Purpose Event Enable Register
114
General-Purpose Input Register
114
General-Purpose Event Enable Register Description
114
General-Purpose Input Register Description
114
General-Purpose Output Register
115
General-Purpose Output Register Description
115
Multifunction Routing Status Register
116
Multifunction Routing Status Register Description
116
Retry Status Register
117
Retry Status Register Description
117
Card Control Register
118
Card Control Register Description
118
Device Control Register
119
Device Control Register Description
119
Diagnostic Register
120
Diagnostic Register Description
120
Capability ID Register
121
Next Item Pointer Register
121
Power Management Capabilities Register
122
Power Management Capabilities Register Description
122
Power Management Control/Status Register
123
Power Management Control/Status Register Description
123
Power Management Control/Status Bridge Support Extensions Register
124
Power Management Control/Status Bridge Support Extensions Register Description
124
Power-Management Data Register
124
Serial Bus Data Register
125
Serial Bus Data Register Description
125
Serial Bus Index Register
125
Serial Bus Index Register Description
125
Default
126
Serial Bus Slave Address Register
126
Serial Bus Slave Address Register Description
126
Serial Bus Control/Status Register
127
Serial Bus Control/Status Register Description
127
Exca Compatibility Registers (Functions 0 and 1)
129
Exca Register Access through I/O
130
Exca Register Access through Memory
130
Exca Registers and Offsets
131
Exca Identification and Revision Register
133
Exca Identification and Revision Register Description
133
Exca Interface Status Register
134
Exca Interface Status Register Description
134
Exca Power Control Register
135
Exca Power Control Register Description—82365Sl Support
135
Exca Power Control Register Description—82365Sl-DF Support
135
Exca Interrupt and General Control Register
136
Exca Interrupt and General Control Register Description
136
Exca Card Status-Change Register
137
Exca Card Status-Change Register Description
137
Exca Card Status-Change Interrupt Configuration Register
138
Exca Card Status-Change Interrupt Configuration Register Description
138
Exca Address Window Enable Register
139
Exca Address Window Enable Register Description
139
Exca I/O Window Control Register
140
Exca I/O Window Control Register Description
140
Exca I/O Windows 0 and 1 Start-Address High-Byte Registers
141
Exca I/O Windows 0 and 1 Start-Address Low-Byte Registers
141
Exca I/O Windows 0 and 1 End-Address High-Byte Registers
142
Exca I/O Windows 0 and 1 End-Address Low-Byte Registers
142
Exca Memory Windows 0−4 Start-Address Low-Byte Registers
143
Exca Memory Windows 0−4 Start-Address High-Byte Registers
144
Exca Memory Windows 0−4 Start-Address High-Byte Registers Description
144
Exca Memory Windows 0−4 End-Address Low-Byte Registers
145
Exca Memory Windows 0−4 End-Address High-Byte Registers
146
Exca Memory Windows 0−4 End-Address High-Byte Registers Description
146
Exca Memory Windows 0−4 Offset-Address Low-Byte Registers
147
Exca Memory Windows 0−4 Offset-Address High-Byte Registers
148
Description
148
Exca Card Detect and General Control Register
149
Exca Card Detect and General Control Register Description
149
Exca Global Control Register
150
Exca Global Control Register Description
150
Exca I/O Windows 0 and 1 Offset-Address High-Byte Registers
151
Exca I/O Windows 0 and 1 Offset-Address Low-Byte Registers
151
Exca Memory Windows 0−4 Page Registers
152
Accessing Cardbus Socket Registers through PCI Memory
153
Cardbus Socket Registers
153
Socket Event Register
154
Socket Event Register Description
154
Socket Mask Register
155
Socket Mask Register Description
155
Socket Present State Register
156
Socket Present State Register Description
156
Socket Force Event Register
157
Socket Force Event Register Description
158
Socket Control Register
159
Socket Control Register Description
159
Socket Power Management Register
160
Socket Power Management Register Description
160
OHCI Controller Programming Model
161
Function 2 Configuration Register Map
161
Device ID Register
162
Vendor ID Register
162
Bit
163
Default: 0000H
163
Intx Assertion Is Enabled (Default)
163
Offset: 04H
163
Register: Command
163
RSVD R Reserved. Bits 15−11 Return 0S When Read
163
Specialr
163
Therefore, Bit 3 Returns 0 When Read
163
Therefore, Bit 5 Returns 0 When Read
163
Type: Read/Write, Read-Only
163
Status Register Description
164
Class Code and Revision ID Register
165
Latency Timer and Class Cache Line Size Register
165
Class Code and Revision ID Register Description
165
Latency Timer and Class Cache Line Size Register Description
165
Header Type and bist Register
166
Header Type and bist Register Description
166
OHCI Base Address Register
166
OHCI Base Address Register Description
166
TI Extension Base Address Register
167
TI Base Address Register Description
167
Cardbus CIS Base Address Register
168
Cardbus CIS Pointer Register
168
Cardbus CIS Base Address Register Description
168
Power Management Capabilities Pointer Register
169
Subsystem Identification Register
169
Subsystem Identification Register Description
169
Interrupt Line Register
170
Interrupt Pin Register
170
Interrupt Line Register Description
170
PCI Interrupt Pin Register—Read-Only INTPIN Per Function
170
Minimum Grant and Maximum Latency Register
171
Minimum Grant and Maximum Latency Register Description
171
OHCI Control Register
171
OHCI Control Register Description
171
Capability ID and Next Item Pointer Registers
172
Capability ID and Next Item Pointer Registers Description
172
Power Management Capabilities Register Description
173
Power Management Control and Status Register
174
Power Management Control and Status Register Description
174
Power Management Extension Registers
174
Power Management Extension Registers Description
174
PCI PHY Control Register
175
PCI PHY Control Register Description
175
PCI Miscellaneous Configuration Register
176
PCI Miscellaneous Configuration Register Description
176
Link Enhancement Control Register
177
Link Enhancement Control Register Description
177
Subsystem Access Register
178
Subsystem Access Register Description
178
GPIO Control Register
179
OHCI Registers
181
OHCI Register Map
181
OHCI Version Register
184
OHCI Version Register Description
184
GUID ROM Register
185
GUID ROM Register Description
185
Asynchronous Transmit Retries Register
186
CSR Data Register
186
Asynchronous Transmit Retries Register Description
186
CSR Compare Register
187
CSR Control Register
187
CSR Control Register Description
187
Bus Identification Register
188
Configuration ROM Header Register
188
Configuration ROM Header Register Description
188
Bus Options Register
189
Bus Options Register Description
189
GUID High Register
190
GUID Low Register
190
Configuration ROM Mapping Register
191
Posted Write Address Low Register
191
Configuration ROM Mapping Register Description
191
Posted Write Address Low Register Description
191
Posted Write Address High Register
192
Posted Write Address High Register Description
192
Vendor ID Register
192
Host Controller Control Register
193
Host Controller Control Register Description
193
Self-ID Buffer Pointer Register
194
Self-ID Count Register
195
Self-ID Count Register Description
195
Isochronous Receive Channel Mask High Register
196
Isochronous Receive Channel Mask High Register Description
196
Isochronous Receive Channel Mask Low Register
197
Isochronous Receive Channel Mask Low Register Description
197
Interrupt Event Register
198
Interrupt Event Register Description
198
Interrupt Mask Register
200
Interrupt Mask Register Description
200
Isochronous Transmit Interrupt Event Register
202
Isochronous Transmit Interrupt Event Register Description
202
Isochronous Transmit Interrupt Mask Register
203
Isochronous Receive Interrupt Event Register
204
Isochronous Receive Interrupt Event Register Description
204
Initial Bandwidth Available Register
205
Initial Bandwidth Available Register Description
205
Isochronous Receive Interrupt Mask Register
205
Initial Channels Available High Register
206
Initial Channels Available High Register Description
206
Initial Channels Available Low Register
206
Initial Channels Available Low Register Description
206
Fairness Control Register
207
Fairness Control Register Description
207
Link Control Register
208
Link Control Register Description
208
Node Identification Register
209
Node Identification Register Description
209
PHY Control Register Description
210
PHY Layer Control Register
210
Isochronous Cycle Timer Register
211
Isochronous Cycle Timer Register Description
211
Asynchronous Request Filter High Register
212
Asynchronous Request Filter High Register Description
212
Asynchronous Request Filter Low Register
214
Asynchronous Request Filter Low Register Description
214
Physical Request Filter High Register
215
Physical Request Filter High Register Description
215
Physical Request Filter Low Register
217
Physical Request Filter Low Register Description
217
Physical Upper Bound Register (Optional Register)
217
Asynchronous Context Control Register
218
Asynchronous Context Control Register Description
218
Asynchronous Context Command Pointer Register
219
Asynchronous Context Command Pointer Register Description
219
Isochronous Transmit Context Control Register
220
Isochronous Transmit Context Control Register Description
220
Isochronous Receive Context Control Register
221
Isochronous Receive Context Control Register Description
221
Isochronous Transmit Context Command Pointer Register
221
Isochronous Receive Context Command Pointer Register
223
Isochronous Receive Context Match Register
224
Isochronous Receive Context Match Register Description
224
TI Extension Registers
225
DV and MPEG2 Timestamp Enhancements
225
TI Extension Register Map
225
Isochronous Receive Digital Video Enhancements
226
Isochronous Receive Digital Video Enhancements Register
226
Isochronous Receive Digital Video Enhancements Register Description
226
Link Enhancement Register
228
Link Enhancement Register Description
228
Timestamp Offset Register
229
Timestamp Offset Register Description
229
PHY Register Configuration
231
Base Registers
231
Base Register Configuration
231
Base Register Field Descriptions
232
Port Status Register
234
Page 0 (Port Status) Register Configuration
234
Page 0 (Port Status) Register Field Descriptions
234
Vendor Identification Register
235
Page 1 (Vendor ID) Register Configuration
235
Page 1 (Vendor ID) Register Field Descriptions
235
Vendor-Dependent Register
236
Page 7 (Vendor-Dependent) Register Configuration
236
Page 7 (Vendor-Dependent) Register Field Descriptions
236
Power-Class Programming
237
Power Class Descriptions
237
Flash Media Controller Programming Model
239
Function 3 Configuration Register Map
239
Device ID Register
240
Vendor ID Register
240
Command Register
241
Command Register Description
241
Status Register
242
Status Register Description
242
Class Code and Revision ID Register
243
Class Code and Revision ID Register Description
243
Latency Timer and Class Cache Line Size Register
243
Latency Timer and Class Cache Line Size Register Description
243
Flash Media Base Address Register
244
Header Type and bist Register
244
Header Type and bist Register Description
244
Flash Media Base Address Register Description
244
Capabilities Pointer Register
245
Subsystem Identification Register
245
Subsystem Vendor Identification Register
245
PCI Interrupt Pin Register
246
Interrupt Line Register
246
Maximum Latency Register
247
Maximum Latency Register Description
247
Minimum Grant Register
247
Minimum Grant Register Description
247
Capability ID and Next Item Pointer Registers Description
248
Power Management Capabilities Register
249
Power Management Capabilities Register Description
249
Power Management Bridge Support Extension Register
250
Power Management Control and Status Register
250
Power Management Control and Status Register Description
250
General Control Register
251
Power Management Data Register
251
Subsystem Access Register Description
252
Diagnostic Register Description
253
SD Host Controller Programming Model
255
Function 4 Configuration Register Map
255
Vendor ID Register
256
Device ID Register
256
Command Register
257
Command Register Description
257
Status Register
258
Status Register Description
258
Class Code and Revision ID Register Description
259
Header Type and bist Register
260
Header Type and bist Register Description
260
Latency Timer and Class Cache Line Size Register Description
260
SD Host Base Address Register
261
SD Host Base Address Register Description
261
Subsystem Vendor Identification Register
261
Capabilities Pointer Register
262
Interrupt Line Register
262
Subsystem Identification Register
262
Minimum Grant Register Description
263
Interrupt Pin Register
263
PCI Interrupt Pin Register
263
Maximum Latency Register
264
Maximum Latency Register Description
264
Slot Information Register
264
Capability ID and Next Item Pointer Registers
265
Capability ID and Next Item Pointer Registers Description
265
Power Management Capabilities Register
266
Power Management Capabilities Register Description
266
Power Management Bridge Support Extension Register
267
Power Management Control and Status Register Description
267
General Control Register
268
Power Management Data Register
268
Diagnostic Register
269
Diagnostic Register Description
269
Subsystem Access Register
269
Subsystem Access Register Description
269
Slot 0 3.3-V Maximum Current Register
270
Slot 1 3.3-V Maximum Current Register
270
Slot 2 3.3-V Maximum Current Register
270
Slot 3 3.3-V Maximum Current Register
271
Slot 4 3.3-V Maximum Current Register
271
Slot 5 3.3-V Maximum Current Register
271
Smart Card Controller Programming Model
273
Function 5 Configuration Register Map
273
Vendor ID Register
274
Device ID Register
274
13.3 Command Register
275
Command Register
275
Command Register Description
275
Status Register
276
Status Register Description
276
Class Code and Revision ID Register
277
Class Code and Revision ID Register Description
277
Latency Timer and Class Cache Line Size Register
277
Latency Timer and Class Cache Line Size Register Description
277
Header Type and bist Register
278
Smart Card Base Address Register 0
278
Header Type and bist Register Description
278
Smart Card Base Address Register 1−4
279
Subsystem Vendor Identification Register
279
Capabilities Pointer Register
280
Interrupt Line Register
280
Subsystem Identification Register
280
Interrupt Pin Register
281
Minimum Grant Register
281
Minimum Grant Register Description
281
PCI Interrupt Pin Register
281
Capability ID and Next Item Pointer Registers
282
Capability ID and Next Item Pointer Registers Description
282
Maximum Latency Register Description
282
Power Management Capabilities Register
283
Power Management Capabilities Register Description
283
Power Management Bridge Support Extension Register
284
Power Management Control and Status Register
284
Power Management Control and Status Register Description
284
General Control Register
285
Power Management Data Register
285
Class Code Alias Register
286
Subsystem ID Alias Register
286
Subsystem ID Alias Register Description
286
Smart Card Configuration 1 Register
287
Smart Card Configuration 2 Register
289
Electrical Characteristics
291
Absolute Maximum Ratings over Operating Temperature Ranges
291
Recommended Operating Conditions
291
Electrical Characteristics over Recommended Operating Conditions
294
Device
295
Driver
295
Electrical Characteristics over Recommended Ranges of Operating Conditions
295
Receiver
295
Test Load Diagram
295
PCI Clock/Reset Timing Requirements over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature
296
Switching Characteristics for PHY Port Interface
296
Operating, Timing, and Switching Characteristics of XI
296
PCI Timing Requirements over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature
296
Mechanical Information
297
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