Power Module Board Description; Analog Interface Board Description - Analog Devices AD8452 User Manual

UG-1181

POWER MODULE BOARD DESCRIPTION

Figure 17 shows the power module board schematic. The input
bus supply connects to the power module board through the J1
connector. MOSFET Q1 is used to connect or disconnect the
input power bus to the switching power section if the input is
within the operating voltage range.
The power module includes input capacitors, a low-side and
high-side MOSFET, an inductor, and output capacitors.
Depending on the mode of operation, the AD8452 drives the
power module in either step-down (buck) or step-up (boost)
mode. The AD8452 drives the power module in synchronous
mode for improved efficiency. A current sense resistor (R14) is
connected in series with the inductor to provide inductor
current feedback to the AD8452 to prevent reverse current.
The ADuM7223 translates the 5 V level PWM signals from the
AD8452 into low impedance, 10 V drive signals for the MOSFETs.
A simple linear regulator circuit on the analog interface board
generates the 10 V rail for the MOSFET driver from the main
input rail.
The power module board includes a 3 mΩ sense resistor (R16)
for measuring the output current. The output of the power
module board connects to the analog interface board through
Connector J3.

ANALOG INTERFACE BOARD DESCRIPTION

The analog interface board includes the AD8452 as well as an
AD5689R DAC to configure the set points and an
ADC to monitor the current and voltage.
The analog interface board includes an
primary inductor converter (SEPIC) to provide a wide input
voltage range followed by a pair of
generate 12 V and 5 V, and an
inverter that generates −5 V for the AD8452 so that it can measure
and output voltages close to 0 V.
The current sense programmable gain instrumentation amplifier
(PGIA) of the AD8452 has a fixed gain of 66. With a gain of 66, a
10 A output current results in an output voltage of 1.98 V at TP6
(Pin ISMEA).
The voltage sense programmable gain difference amplifier
(PGDA) has a fixed gain of 0.4. With a gain of 0.4, a 4 V battery
voltage results in a 1.6 V output at TP13 (Pin BVMEA).
AD7173-8
ADP1612 single-ended
ADP7102 linear regulators to
ADM8829 switched capacitor
AD8452
The AD7173-8
and reports the values to the user interface software through the
SDP-S interface. The default full-scale input range of the
is configured at 2.5 V. The
the constant current set point, and Output B sets the constant
voltage set point. The default DAC output range is also from
0 V to 2.5 V. Given the current and voltage gain settings of the
AD8452, the current and voltage set points can be calculated as
follows:
PGIA_GAIN = 66
PGDA_GAIN = 0.4
Constant_Current_Setpoint = V
Constant_Current_Setpoint = V
The ADCMP370
from nonsynchronous to synchronous switching. When the
output current is less than 1 A, the comparator clamps the SS
pin to less than 4.5 V and forces the AD8452 to operate in
nonsynchronous switching mode. When the output current
exceeds 1 A, the SS pin is allowed to rise above 4.5 V, and the
AD8452 transitions to synchronous switching mode. Operating
in nonsynchronous switching mode at low output currents
effectively eliminates reverse current though the inductor.
At higher currents, synchronous switching provides improved
converter efficiency.
The Q8, Q9, Q10, and Q11 output transistors form a bidirectional
load switch on the output of the dc-to-dc converter. The load
switch is disabled by default with a shorting jumper across JP1.
Removing the shorting jumper across JP1 enables the load
switch and demonstrates how the load switch can control
current direction during low current operation.
The state of the load switch FETs is determined by the operating
mode and the output current. When the
detects that the output current is less than 500 mA, the mode
signal enables one pair of load switch FETs and disables the
second pair of load switch FETs. Current is forced through the
diode in parallel with the disabled FET pair, controlling the
direction of current flow. Additionally, the increased output
impedance of the diode allows enhanced current control when
operating below 500 mA. When the output current exceeds 500
mA, both pairs of load switch FETs are enabled, providing a low
resistance current path and maximum power efficiency.
Rev. 0 | Page 6 of 32
System Demo User Guide
ADC measures the voltage and current signals
AD5689R DAC Output A configures
/(PGIA_GAIN × 0.003)
DAC_A
/(PGDA_GAIN)
DAC_B
comparator at U11 controls the transition
ADCMP370
AD7173-8
at U17