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BASIC TIMER and TIMER 0
TIMER 0 FUNCTION DESCRIPTION
Interval Timer Mode
In interval timer mode, a match signal is generated when the counter value is identical to the value written to the
Timer 0 reference data register, T0DATA. The match signal generates a Timer 0 match interrupt (T0INT, vector
00H) and then clears the counter. If, for example, you write the value "10H" to T0DATA, the counter will increment
until it reaches "10H". At this point, the Timer 0 interrupt request is generated, the counter value is reset and
counting resumes.
CLK
NOTE:
Figure 10-5. Simplified Timer 0 Function Diagram (Interval Timer Mode)
10-8
Counter (T0CNT)
Comparator
Data Register (T0DATA)
T0CON.3 is not auto-cleared, you must pay attention when clear pending bit
(refer to P10-12)
T0CON.3
R (clear)
Timer 0 counter clear
Match
PND
Interrupt Enable/Disable
S3C9454B/F9454B
IRQ0 (T0INT)
T0CON.1
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