Calibrating The Sync Delay Using An Spectrum Analyzer - Texas Instruments TSW4100EVM User Manual

www.ti.com
8.6

Calibrating the Sync Delay Using an Spectrum Analyzer

The correct sync delay can be determined by looking at the TSW4100 output with a single input tone that
is set slightly off center of the band center.
Consider the example presented in
2:
This means that two GC5016 input clock cycles (at 160 MHz) are used for 1 interface clock cycle (80
MHz). See the GC5016 Input Output Mode Application Note (SLWA037) for details on the interleave IQ
interface.
For proper data transfer, align the DDC output and DUC input timing to look like
With a decimation/interpolation of 8, there are 8 possible phases between the DDC output data and DUC
input timing. With the interface clock ratio of 2, I and Q are held for two input clock cycles. For the DUC
input, the I latch and Q latch occur 2 input clock cycles apart. By adjusting the sync delay, find the
appropriate timing for the channel. This is represented in
and the 8 possible Sync phases of the DUC are shown.
Clock DDC
Cycle output
Phase 1
1 —
2 —
3 —
4 —
5 I
6 I
7 Q
8 Q
Good/Bad
Result
Tones
The correct value of the sync delay is dependent on decimation, filter mode, filter length, etc. and is
deterministic and repeatable. As is seen in
case, both I and Q are correctly transferred and a single tone in the spectram above is observed.
However, it cannot be predicted ahead of time. For the TSW4100 example above, a value '5' should be
correct. However, a design flaw in the timing for the TSW4100 (there is board to board latency uncertainty
in the crystal filter for the ADC) means some boards may have slightly different values – this will be
corrected in a revised version.
As an example, consider the configuration described above with the decimation ratio is 8, with an input
tone offset from the center of the channel. There are 4 phases where only I or Q are transferred (and
swapped). Observing the output of these 4 phases, this results in two tones with 6 dB lower power:
SLWU052A – December 2007 – Revised September 2008
Submit Documentation Feedback
Section
Phase 2 Phase 3
I latch — —
— I latch —
Q latch I latch
— Q latch
— — Qlatch
— —
— —
— —
Bad Bad Bad
0 0
Table
8.5. In the interface settings, the interface clock ratio is set to
Table 6, where each row is an input clock cycle
Table 6.
DUC Input
Phase 4 Phase 5
— —
— —
— —
I latch —
— I latch
- Qlatch —
- — Q latch
- — —
Bad Good
2 2 1
6, there are two phases that should be "good". In this
Programming the TSW4100
Figure 62.
Phase 5 Phase 7 Phase 8
— Q latch
— — Q latch
— —
— —
— —
I latch —
— I latch
Q latch — I latch
Good Bad Bad
1 2
TSW4100EVM
—
—
—
—
—
—
2
49