Texas Instruments TSW1200EVM User Manual
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Texas Instruments TSW1200EVM User Manual

High-speed lvds deserializer and analysis system
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TSW1200EVM: High-Speed LVDS Deserializer and
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SLAU212A - April 2007 - Revised August 2008
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SLAU212A - April 2007 - Revised August 2008
Contents
List of Figures
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List of Tables
TSW1200EVM: High-Speed LVDS Deserializer and Analysis System
User's Guide
Analysis System
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Summary of Contents for Texas Instruments TSW1200EVM

  • Page 1: Table Of Contents

    TSW1200C Layout Layer 5 ......................TSW1200C Layer 6 ....................TSW1200C Bottom Layer ...................... Circuit Board Stackup List of Tables ......................Bill of Materials SLAU212A – April 2007 – Revised August 2008 TSW1200EVM: High-Speed LVDS Deserializer and Analysis System Submit Documentation Feedback...
  • Page 2 LabVIEW is a trademark of National Instruments Corporation. MATLAB is a trademark of The MathWorks, Inc.. Xilinx is a trademark of Xilinx, Inc.. TSW1200EVM: High-Speed LVDS Deserializer and Analysis System SLAU212A – April 2007 – Revised August 2008 Submit Documentation Feedback...

  • Page 3: Introduction

    The TSW1200 hardware has a high-speed connector that plugs into an evaluation module (EVM) for the ADC. Firmware for an FPGA on the TSW1200EVM has an interface to various LVDS data formats and FIFO memory sufficient to capture as much as 64K samples of data. A USB connection transfers the captured data to a personal computer for post-processing.
  • Page 4 UART function that can transfer data to and from a USB interface device on the TSW1200 board. The USB interface device on the TSW1200EVM connects to a personal computer (PC) running Windows™ over a standard USB cable. The operation of the FIFO capture logic is controlled by writes from the PC USB port to a register map defined within the FPGA.

  • Page 5: Hardware Configuration

    In this section, the various portions of the TSW1200EVM hardware are described. Power Connections The TSW1200EVM hardware is designed to operate from a single-supply voltage of greater than 6 Vdc. For convenience, two options can supply power to the TSW1200EVM. A bench power supply can supply power to banana jack connections on the TSW1200EVM, or a laptop-style power module that is included with the TSW1200 hardware can supply power.
  • Page 6 A low drop-out linear power regulator on the TSW1200EVM generates a clean, low-noise 5-V supply from the 6-V power that is input to the TSW1200EVM. The jumper J22 can be used to connect this onboard regulated 5 V to the red banana jack J15 as an output. This option is a convenience for use with ADC EVMs that require a single 5-V supply input.

  • Page 7: Position Of Switches And Jumpers

    JTAG connector pin TDO through jumper J1 pins 1-2. If it desired to remove either the PFGA or the FPGA EEPROM from the JTAG chain, the jumpers J1 or J12 can be turned 90 degrees to connect pins 1-2 and 3-4. See the TSW1200EVM schematics and layout sections for illustration of this option.

  • Page 8: Eeprom Configuration Options

    LEDs Six LEDs are on the TSW1200EVM to indicate the presence of power and the state of the FPGA. See Figure 4. LED D16 illuminates to indicate the presence of a 6-V power supply to the board. On power up, the FPGA loads its programming bit file from the FPGA EEPROM.

  • Page 9: Position Of Leds

    3.4.1 Samtec LVDS Connector The connection between the TSW1200EVM and the ADC EVM to be tested is through a 120-pin Samtec connector. Fourteen LVDS data pairs plus two LVDS clock pairs have a defined position in the connector pinout that is common between the TSW1200EVM and many TI ADC EVMs. For the parallel LVDS DDR data format, the bit clock runs at the same rate as the sample clock to the ADC.
  • Page 10 ADC EVM together. The TSW1200EVM comes with standoff posts for setting the TSW1200EVM flat on a bench or table. The ADC EVM has shorter standoff posts so that the TSW1200EVM and ADC EVM will lay flat on a bench or table and stay snapped together during use.

  • Page 11: Position Of Input, Output, And Usb Connections

    CMOS single-ended data on output header posts, or a set record length of ADC parallel data samples can be captured in the TSW1200EVM FIFOs and output to a PC through the USB serial port. The data capture by the FIFOs and TSW1200 user interface is the most convenient way to capture data from an ADC, but sometimes the continuous stream of data is desirable.

  • Page 12: Software Installation

    (VCP) and shows up in the Hardware Device Manager as TSW1200 under COM ports and as TSW1200 EVM under Multi-Port Serial Adapters. See Figure 8. On the TSW1200EVM, the USB port acts as a bridge to UART control of the FPGA. Control of the FPGA is managed by reads and writes to a register map of control registers defined in the design of the FPGA.

  • Page 13: Tsw1200 User Interface Installation

    Microsoft XP operating system. Included on the installation CD is this user’s guide, a setup program to install the user interface software, and a suite of MATLAB™ routines that can be used to interface to the TSW1200EVM hardware. All drivers necessary for the USB connection and the user interface software are included.

  • Page 14: Hardware Device Manager

    USB Port and Drivers When the Virtual Com Port is installed and the USB cable has connected the TSW1200EVM to the PC, the TSW1200 can be located in the Hardware Device Manager as shown in Figure 8.

  • Page 15: Found New Hardware Windows

    When the TSW1200EVM USB cable is unplugged and plugged in again to a different USB port on the computer, the Found New Hardware Wizard may appear again, depending on whether that USB port is controlled by a different USB controller in the computer and depending on the registry configuration for the PC.

  • Page 16: User Interface

    The use of ini files allows for new device types to be supported by the TSW1200EVM as they become available without having to modify, re-release, or re-install the TSW1200 user interface software. New device types may be supported at a later date simply by adding a new ini file to the proper subdirectory, using a script that TI will make available at that time.
  • Page 17 The UART baud rate can be set to one of four data rates. This controls the data rate of unloading the FIFO capture from the TSW1200EVM FPGA to the USB port. The UART baud rate is the limiting factor for the time it takes to capture long record lengths of data.
  • Page 18 If an ADC selection is made that is not supported by the TSW1200EVM jumper settings of J10 and J11, then a message in the status window prompts the user for a different device selection or to set the jumpers to the proper position on the hardware.
  • Page 19 Rectangular can be used to process out this effect to some degree. The FFT record length can be set in the FFT Record Length (NS) input text box. The TSW1200EVM supports FFT record lengths of as much as 65536 samples, or as little as 4096 samples.

  • Page 20: User Interface Single Fft Format

    Settings and inputs relevant to the test are entered in drop-down menus or text input boxes on the left portion of the window. TSW1200EVM: High-Speed LVDS Deserializer and Analysis System SLAU212A – April 2007 – Revised August 2008 Submit Documentation Feedback...
  • Page 21 When done in this order, the coherent input frequency is carried over to the Time Domain test. The FFT record length can be set in the FFT Record Length (NS) input text box. The TSW1200EVM supports FFT record lengths of as much as 65536 samples, or as little as 4096 samples.

  • Page 22: Matlab™ Interface

    MATLAB routines to process the data record captured by the TSW1200EVM FIFOs. Included on the Installation CD for the TSW1200EVM is a directory of files for an alternative MATLAB interface to the TSW1200EVM. This MATLAB code is a functional starting point for communicating with the TSW1200 hardware and capturing data from a number of TI ADCs.

  • Page 23: Schematics And Bill Of Materials

    Schematics and Bill of Materials www.ti.com Schematics and Bill of Materials Schematics Figure 13. Schematic Diagram Page 1 SLAU212A – April 2007 – Revised August 2008 TSW1200EVM: High-Speed LVDS Deserializer and Analysis System Submit Documentation Feedback...

  • Page 24: Schematic Diagram

    Schematics and Bill of Materials www.ti.com Figure 14. Schematic Diagram Page 2 TSW1200EVM: High-Speed LVDS Deserializer and Analysis System SLAU212A – April 2007 – Revised August 2008 Submit Documentation Feedback...

  • Page 25: Schematic Diagram

    Schematics and Bill of Materials www.ti.com Figure 15. Schematic Diagram Page 3 SLAU212A – April 2007 – Revised August 2008 TSW1200EVM: High-Speed LVDS Deserializer and Analysis System Submit Documentation Feedback...

  • Page 26: Schematic Diagram

    Schematics and Bill of Materials www.ti.com Figure 16. Schematic Diagram Page 4 TSW1200EVM: High-Speed LVDS Deserializer and Analysis System SLAU212A – April 2007 – Revised August 2008 Submit Documentation Feedback...

  • Page 27: Schematic Diagram

    Schematics and Bill of Materials www.ti.com Figure 17. Schematic Diagram Page 5 SLAU212A – April 2007 – Revised August 2008 TSW1200EVM: High-Speed LVDS Deserializer and Analysis System Submit Documentation Feedback...

  • Page 28: Bill Of Materials

    897-43-004-90-000 Milmax CONN_QSH_30X2-D-A conn_QSH_30X2-D-A QSH-060-01-F-D-A Samtec J10, J11 Header 3 jumper3 22-28-4030 Molex Short pins 1-2 with shunt connector DigiKey # S9000-ND TSW1200EVM: High-Speed LVDS Deserializer and Analysis System SLAU212A – April 2007 – Revised August 2008 Submit Documentation Feedback...
  • Page 29 Microchip Socket, dip 8 DIP8_3 ED58083-ND DigiKey TPS76750QPWP HTSSOP_20_260x177_26_pwr TPS76750QPWP TI Provide LV7745DEV-200MHz SMD_XTAL_7X5MM_6PIN LV7745DEV-200MHz Pletronics U11,U13 TPS76733QPWP HTSSOP_20_260x177_26_pwr TPS76733QPWP TI Provide SLAU212A – April 2007 – Revised August 2008 TSW1200EVM: High-Speed LVDS Deserializer and Analysis System Submit Documentation Feedback...

  • Page 30: Circuit Board Layout And Layer Stackup

    Building Fasteners legs Standoff RD 4-40 THR 1846 Keystone 0.875" ALUM Circuit Board Layout and Layer Stackup Figure 18. TSW1200C Layout Top Layer TSW1200EVM: High-Speed LVDS Deserializer and Analysis System SLAU212A – April 2007 – Revised August 2008 Submit Documentation Feedback...

  • Page 31: Tsw1200C Layout Layer Two

    Circuit Board Layout and Layer Stackup www.ti.com Figure 19. TSW1200C Layout Layer Two SLAU212A – April 2007 – Revised August 2008 TSW1200EVM: High-Speed LVDS Deserializer and Analysis System Submit Documentation Feedback...

  • Page 32: Tsw1200C Layout Power Plane

    Circuit Board Layout and Layer Stackup www.ti.com Figure 20. TSW1200C Layout Power Plane TSW1200EVM: High-Speed LVDS Deserializer and Analysis System SLAU212A – April 2007 – Revised August 2008 Submit Documentation Feedback...

  • Page 33: Tsw1200C Layout Ground Plane

    Circuit Board Layout and Layer Stackup www.ti.com Figure 21. TSW1200C Layout Ground Plane SLAU212A – April 2007 – Revised August 2008 TSW1200EVM: High-Speed LVDS Deserializer and Analysis System Submit Documentation Feedback...

  • Page 34: Tsw1200C Layout Layer 5

    Circuit Board Layout and Layer Stackup www.ti.com Figure 22. TSW1200C Layout Layer 5 TSW1200EVM: High-Speed LVDS Deserializer and Analysis System SLAU212A – April 2007 – Revised August 2008 Submit Documentation Feedback...

  • Page 35: Tsw1200C Layer

    Circuit Board Layout and Layer Stackup www.ti.com Figure 23. TSW1200C Layer 6 SLAU212A – April 2007 – Revised August 2008 TSW1200EVM: High-Speed LVDS Deserializer and Analysis System Submit Documentation Feedback...

  • Page 36: Tsw1200C Bottom Layer

    Circuit Board Layout and Layer Stackup www.ti.com Figure 24. TSW1200C Bottom Layer TSW1200EVM: High-Speed LVDS Deserializer and Analysis System SLAU212A – April 2007 – Revised August 2008 Submit Documentation Feedback...

  • Page 37: Circuit Board Stackup

    Circuit Board Layout and Layer Stackup www.ti.com Figure 25. Circuit Board Stackup SLAU212A – April 2007 – Revised August 2008 TSW1200EVM: High-Speed LVDS Deserializer and Analysis System Submit Documentation Feedback...
  • Page 38 EVALUATION BOARD/KIT IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards.
  • Page 39 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
  • Page 40 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Texas Instruments TSW1200EVM...

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