Texas Instruments TSW4100EVM User Manual
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Texas Instruments TSW4100EVM User Manual

Texas Instruments TSW4100EVM User Manual

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1
2
2.1
2.2
3
3.1
3.2
3.3
4
4.1
4.2
4.3
4.4
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5.1
5.2
5.3
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6.1
6.2
6.3
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7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
8
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
EP2C8 Cyclone II, EPCS4, ByteBlaster II, Quartus II are trademarks of Altera Corporation.
SLWU052A - December 2007 - Revised September 2008
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SLWU052A - December 2007 - Revised September 2008
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User's Guide
TSW4100EVM
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TSW4100EVM
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Summary of Contents for Texas Instruments TSW4100EVM

  • Page 1: Table Of Contents

    User's Guide SLWU052A – December 2007 – Revised September 2008 TSW4100EVM Contents ........................Introduction ......................TSW4100 Interfaces ......................USB Port J26 ....................USB Connector J25 ..................... Hardware Configuration ....................Power Requirements ..................... Jumper Settings ....................Apply Power to Board ......................
  • Page 2 ................ TSW4100 Interface with Filter Design Settings ................... Filter Design Output Spectrum ..............Proper DDC Output and DUC Input Timing Alignment ......................DUC Input Time ........................Test Points TSW4100EVM SLWU052A – December 2007 – Revised September 2008 Submit Documentation Feedback...

  • Page 3: Contents 1 Introduction

    RX outputs or provide inputs to the TX portion of the chain. The TSW4100 requires only a single 5-6 V DC power source at 3 A to operate. The block diagram of the TSW4100 is shown in Figure SLWU052A – December 2007 – Revised September 2008 TSW4100EVM Submit Documentation Feedback...

  • Page 4: Tsw4100 Block Diagram

    Introduction www.ti.com Figure 1. TSW4100 Block Diagram TSW4100EVM SLWU052A – December 2007 – Revised September 2008 Submit Documentation Feedback...

  • Page 5: Tsw4100 Interfaces

    Clock provided from VCXO U19 Input clock provided from J20 ADS5545 output enable Output enabled Output disabled SJP3 ADS5545 output clock direction Sends output clock to DDC Sends output clock to FPGA SLWU052A – December 2007 – Revised September 2008 TSW4100EVM Submit Documentation Feedback...

  • Page 6: Apply Power To Board

    Installing the TSW4100 interface to the GC5016 CDC and DAC Software • Section 4.2 Installing the USB Driver Software • Section 4.3 Installing the MATLAB Runtime Engine • Section 4.4 Installing the TSW4100GUI Software TSW4100EVM SLWU052A – December 2007 – Revised September 2008 Submit Documentation Feedback...

  • Page 7: Installing The Tsw4100 Interface To Gc5016 Cdc And Dac Software

    4. If asked, click on the Don't' search. I will choose the driver to install option. 5. If a window opens with the following driver name Texas Instruments TSW4100 DAC and CDC Controller, select this then click next. If this does not appear, navigate to the C:\Program Files\TSW4100_DAC_CDC\TSW4100 Drivers directory.

  • Page 8: Installing The Matlab Runtime Engine

    3) displays, click Next. Figure 3. MATLAB Welcome Screen 3. For the Customer Information (Figure 4) screen, specify the User Name, Organization, select the desired user option button, and click Next. TSW4100EVM SLWU052A – December 2007 – Revised September 2008 Submit Documentation Feedback...

  • Page 9: Customer Information

    Figure 5. Destination Folder 5. When the Ready to Install the Program screen (Figure 6) displays, click Install to begin the installation. The installation lasts approximately five minutes. SLWU052A – December 2007 – Revised September 2008 TSW4100EVM Submit Documentation Feedback...

  • Page 10: Ready To Install The Program

    Software Installation www.ti.com Figure 6. Ready to Install the Program 6. Click Finish once the InstallShield Wizard Completed screen (Figure 7) displays. Figure 7. InstallShield Wizard Completed TSW4100EVM SLWU052A – December 2007 – Revised September 2008 Submit Documentation Feedback...

  • Page 11: Installing The Tsw4100Gui Software

    9) displays, select the I accept the terms in the License agreement option and click Next to accept the TSW4100 Software License Agreement. Figure 9. TSW4100 License Agreement SLWU052A – December 2007 – Revised September 2008 TSW4100EVM Submit Documentation Feedback...

  • Page 12: Customer Information

    Install this Application for option. Click Next. Figure 10. Customer Information 4. On the Setup Type (Figure 11) display, select the Complete Setup Type option and click Next. Figure 11. Setup Type TSW4100EVM SLWU052A – December 2007 – Revised September 2008 Submit Documentation Feedback...

  • Page 13: Ready To Install The Program

    Figure 12. Ready to Install the Program 6. Click Finish once the InstallShield Wizard Completed screen (Figure 13) displays. Figure 13. InstallShield Wizard Completed SLWU052A – December 2007 – Revised September 2008 TSW4100EVM Submit Documentation Feedback...

  • Page 14: Running The Tsw4100 Cdc And Dac Interface

    Starting the TSW4100 Interface The TSW4100 software is now ready to use. To start the application program, click the Windows menu sequence start → All Programs → Texas Instruments TSW4100 DAC and CDC Control → TSW4100 DAC and CDC Control (Figure 14).

  • Page 15: Loading The Cdcm7005 With Default Values

    8. The default values are also stored in a file provided by TI. To load the stored settings, click the Load Settings button on the lower left side of the GUI. SLWU052A – December 2007 – Revised September 2008 TSW4100EVM Submit Documentation Feedback...

  • Page 16: Loading The Dac5688

    The default values for the DAC5688 and CDCM7005 are stored in a file provided by TI. To load the stored settings, click the Load Settings button on the lower left side of the GUI. Navigate to the directory (C:\Program Files\Texas Instruments\TSW4100GUI\CDCandDACregisters\) and select the file TSW4100_DAC_CDC_example_1.txt. The GUI loads both the DAC5688 and CDCM7005 with the settings contained in this file every time the Load Settings function is used.

  • Page 17: Dac5688 Interface

    11. Click on the Read All button, located on the top right side of the GUI, to view the current register settings of the DAC5688. If an error message is not received, the program is working properly. Figure 16. DAC5688 Interface SLWU052A – December 2007 – Revised September 2008 TSW4100EVM Submit Documentation Feedback...

  • Page 18: Dac5688 Options

    Running the TSW4100 CDC and DAC Interface www.ti.com Figure 17. DAC5688 Options Figure 18. DAC5688 Filters TSW4100EVM SLWU052A – December 2007 – Revised September 2008 Submit Documentation Feedback...

  • Page 19: Clock Settings

    Running the TSW4100 CDC and DAC Interface www.ti.com Figure 19. Clock Settings Figure 20. DAC Gain SLWU052A – December 2007 – Revised September 2008 TSW4100EVM Submit Documentation Feedback...

  • Page 20: Tsw4100 Graphical User Interface (Gui) Software

    Note: To interface with the TSW4100, the CDCM7005 must be operating and locked. To start the TSW4100GUI interface: 1. Click the Windows menu sequence start → All Programs → Texas Instruments → TSW4100GUI → TSW4100GUI_vXpXX.exe, (Figure 14) where vXpxx represents the version of software. The application first displays a DOS Test Window.

  • Page 21: Tsw4100Gui Dos Test Window

    If the TSW4100 GUI display does not fit on the user's monitor, a second version of the GUI can be loaded which reduces the size of the GUI. This executable is called TSW4100GUI_vXpXX_resize.exe and can be found at C:\Program Files\Texas Instruments\TSW4100GUI. SLWU052A – December 2007 – Revised September 2008 TSW4100EVM Submit Documentation Feedback...

  • Page 22: Graphical User Interface Controls

    Left Column area The user interface controls (Figure 26) on the left side of the screen control major functionality settings and the content of the output filter response displays. TSW4100EVM SLWU052A – December 2007 – Revised September 2008 Submit Documentation Feedback...

  • Page 23: Left Column Interface Controls

    The mixed mode Ch ＝ = SPLIT IQ and Ch 3/4 = 4 CHANNEL is invalid. In this case, swap Ch ＝ and Ch 3/4 option selections. Figure 27. Channel Selection Controls SLWU052A – December 2007 – Revised September 2008 TSW4100EVM Submit Documentation Feedback...

  • Page 24: Channel Configuration Controls

    Taps = PFIR –number of CIC compensation taps +1. (See raw filter Max Taps Section 7.8 for more information and examples of CIC compensation taps design.) TSW4100EVM SLWU052A – December 2007 – Revised September 2008 Submit Documentation Feedback...

  • Page 25: Filter Load And Design Settings

    • Sync Delay—delay in DDC to DUC syncs. After TSW4100 is programmed, check real time sync for a new sync to be issued for the channel each time this is changed. SLWU052A – December 2007 – Revised September 2008 TSW4100EVM Submit Documentation Feedback...

  • Page 26: Filter Response Windows

    The stopband amplitudes are one half the input values, as the DDC and DUC filter operate in series, doubling the attenuation. The final band, which is the image band, is 1× the final stopband amplitude. These figures also include the image bands. TSW4100EVM SLWU052A – December 2007 – Revised September 2008 Submit Documentation Feedback...

  • Page 27: Designing And Testing A Filter (Step-By-Step)

    The TSW4100 GUI can be used stand alone (not connected to the TSW4100) to do filter design or generate the DUC and DDC configuration. Step 1—Start TSW4100GUI Click the Windows menu sequence start → All Programs → Texas Instruments → TSW4100GUI → TSW4100GUI.exe to start the TSW4100GUI. SLWU052A – December 2007 – Revised September 2008...

  • Page 28: Step 2-Channel Selection

    Equation d. Set the Stopband Amps (dB) to 50. Stopband Frequency = Passband BW÷2 + Bandedge Frequency = 12÷2 + .5 = 6.5 Figure 34. Filter Design Parameters TSW4100EVM SLWU052A – December 2007 – Revised September 2008 Submit Documentation Feedback...

  • Page 29: Step 4-Saving Filter Design Information

    First, look at Figure 36. This plot shows the PFIR spectral response of the DUC (TX) and DDC (RX) before convolution with CIC correction taps (using 3 or 5 taps). SLWU052A – December 2007 – Revised September 2008 TSW4100EVM Submit Documentation Feedback...
  • Page 30 CIC decimation and interpolation filter. CH1 PFIR Response: Convolved RX and TX PFIRs ripple = 0.9872 band2 = 50.9517 band3 = 100.7474 f - Frequency - MHz Figure 37. Composite Frequency Response TSW4100EVM SLWU052A – December 2007 – Revised September 2008 Submit Documentation Feedback...

  • Page 31: Step 7-Examine The Filter Response Passband

    DUC and DDC PFIR design; not including the CIC compensation and CIC. This allows no margin for incomplete CIC compensation, which is discussed in section Section 7.8. SLWU052A – December 2007 – Revised September 2008 TSW4100EVM Submit Documentation Feedback...

  • Page 32: Step 8-Evaluate Effect Of Taps On Filter Latency

    96 taps. This is done to minimize the latency of the filter. The PFIR coefficient memory locations for taps 60 to 96 (Figure 41) are set to zero. TSW4100EVM SLWU052A – December 2007 – Revised September 2008 Submit Documentation Feedback...

  • Page 33: Step 9-Redesign By Decreasing The Cic Decimation

    Now modify the Channel 1 filter design to include less CIC decimation. Reset the CIC rate to 4 and click on the "Configure " button(Figure 42) The maximum number of PFIR taps is reduced to 127, when the CIC rate is reduced. Figure 42. Redesigned Filter Settings SLWU052A – December 2007 – Revised September 2008 TSW4100EVM Submit Documentation Feedback...
  • Page 34 31, measure it at 1.12 dB or 0.1 dB greater than the design requirement. CH1 PFIR Response: Convolved RX and TX PFIRs -0.2 -0.4 -0.6 -0.8 f - Frequency - MHz Figure 44. Redesigned Filter Passband TSW4100EVM SLWU052A – December 2007 – Revised September 2008 Submit Documentation Feedback...

  • Page 35: 7.10 Step 10-Redesign By Changing The Filter Parameters

    CH1 PFIR Response: Convolved RX and TX PFIRs -0.5 f - Frequency - MHz Figure 46. Passband of Successful Filter Design SLWU052A – December 2007 – Revised September 2008 TSW4100EVM Submit Documentation Feedback...
  • Page 36 PFIR coefficient memory space. This implies the latency is fixed, regardless of the number of PFIR taps in the design (up to the maximum). Figure 48. Filter Latency TSW4100EVM SLWU052A – December 2007 – Revised September 2008 Submit Documentation Feedback...

  • Page 37: Programming The Tsw4100

    80 to 160 MHz Nyquist band of the ADC. Removing unwanted output harmonics is described later in Section 8.7. Connect the DAC output SMA to a spectrum analyzer. SLWU052A – December 2007 – Revised September 2008 TSW4100EVM Submit Documentation Feedback...

  • Page 38: Program Clock Pll And Dac

    6. Now program the DAC5688 normal operation as described in Section 5.3 by changing the output format back to two’s complement. This should result in removing the tone. TSW4100EVM SLWU052A – December 2007 – Revised September 2008 Submit Documentation Feedback...

  • Page 39: Programming The Duc And Ddcs

    –10 dBm, reflecting 7 dB loss between the ADC and DAC full scale and another 3 dB loss due to cables, transformers, and so forth. SLWU052A – December 2007 – Revised September 2008 TSW4100EVM Submit Documentation Feedback...

  • Page 40: Setting The Sync Delay For A Channel

    DDC and DUC to align the DDC output I and Q samples to the DUC input I and Q samples. Figure 53. Proper DDC Output and DUC Input Timing Alignment TSW4100EVM SLWU052A – December 2007 – Revised September 2008 Submit Documentation Feedback...
  • Page 41 For a CIC decimation of > 8 (overall decimation of 16), it is recommended to use the oscilloscope method. SLWU052A – December 2007 – Revised September 2008 TSW4100EVM Submit Documentation Feedback...

  • Page 42: Calibrating The Sync Delay Using An Oscilloscope

    Loops Pads FPGA Loops Figure 55. Test Points Starting with Channel 1, connect 3 probes to AFS, ACK and A0. The oscilloscope display should look like this: TSW4100EVM SLWU052A – December 2007 – Revised September 2008 Submit Documentation Feedback...
  • Page 43 16, or 6×16 = 96 high speed clock cycles by setting the sync delay to 96 and pressing the sync button. This should result in a shifting of the data A0 to divided clock cycles after AFS, as shown in the oscilloscope display in Figure SLWU052A – December 2007 – Revised September 2008 TSW4100EVM Submit Documentation Feedback...
  • Page 44 1 divided clock cycle), change the SCK polarity for channel 1 to negative and resync. This should shift the data to the appropriate time as shown in the oscilloscope display in Figure TSW4100EVM SLWU052A – December 2007 – Revised September 2008 Submit Documentation Feedback...
  • Page 45 Using the default settings from the configuration file loaded previously and connecting the oscilloscope to CFS, CCK and C0, the user finds that the data is again out of timing alignment with the framestrobe (Figure 59): SLWU052A – December 2007 – Revised September 2008 TSW4100EVM Submit Documentation Feedback...
  • Page 46 Figure 59. Starting Interface Timing for Channel 3 By trial and error, it is determined that the ideal sync delay is 129, which results in the following oscilloscope display shown in Figure TSW4100EVM SLWU052A – December 2007 – Revised September 2008 Submit Documentation Feedback...
  • Page 47 The oscilloscope method can also be used with much lower decimation rates. For example, with a total decimation of 6 and a SCK divider ratio of 2, Figure 61 Figure 62 show examples of incorrect and correct interface timing: SLWU052A – December 2007 – Revised September 2008 TSW4100EVM Submit Documentation Feedback...
  • Page 48 Figure 61. Incorrect Interface Timing for a Decimation of 6 and SCK Divider Ratio of 2 Figure 62. Correct Interface Timing for a Decimation of 6 and SCK Divider Ratio of 2 TSW4100EVM SLWU052A – December 2007 – Revised September 2008...

  • Page 49: Calibrating The Sync Delay Using An Spectrum Analyzer

    There are 4 phases where only I or Q are transferred (and swapped). Observing the output of these 4 phases, this results in two tones with 6 dB lower power: SLWU052A – December 2007 – Revised September 2008 TSW4100EVM Submit Documentation Feedback...
  • Page 50 And finally, there are 2 phases where neither I nor Q are transferred. In this case, there is no tone observed in Figure Figure 64. 2 Phases Where Only I or Q Are Transferred TSW4100EVM SLWU052A – December 2007 – Revised September 2008 Submit Documentation Feedback...

  • Page 51: Requirement For Nyquist Filtering For The Adc

    100 MHz tone, resulting in the highest spur is at –70 dBm. Without the input filter, the highest spur is at –56 dBm, or 14 dB worse. Figure 65. With and Without an ADC Filter to Remove Output Frequency Harmonics SLWU052A – December 2007 – Revised September 2008 TSW4100EVM Submit Documentation Feedback...

  • Page 52: Adding Other Channels

    80 to 160 MHz while the spectrum analyzer has a trace set to MAX HOLD (blue in Figure 67) and a trace set to clear/write (yellow). Clicking the Configure button generates the output (observed after allowing the sweep to complete). TSW4100EVM SLWU052A – December 2007 – Revised September 2008 Submit Documentation Feedback...

  • Page 53: Using Other Nyquist Zones

    3rd Nyquist Zone Example. This setting is saved as C:\Program Files\Texas Instruments\TSW4100GUI\TSW4100example3_config.mat and also on the provided CD. Make sure that the Nyquest Zone is set to "3" before running this example. SLWU052A – December 2007 – Revised September 2008 TSW4100EVM Submit Documentation Feedback...
  • Page 54 Programming the TSW4100 www.ti.com Figure 68. TSW4100GUI Settings to Generate Third Nyquist Zone Figure 69. Third Nyquist Zone Example Output Spectrum TSW4100EVM SLWU052A – December 2007 – Revised September 2008 Submit Documentation Feedback...

  • Page 55: Appendix A Firmware Downloading (If Updates Are Needed)

    Appendix A www.ti.com Appendix A Firmware Downloading (if updates are needed) The TSW4100 contains an Altera EP2C8 Cyclone II™ FPGA device (U10) and an Altera EPCS4 reprogrammable serial configuration device (U13). Upon power application or reset (SW4), the EPCS4 programs the FPGA. If firmware (other than what is delivered with the EVM) is used, either the EPCS4 or the FPGA can be reprogrammed through JTAG connector J14.
  • Page 56 Appendix A www.ti.com Figure A-2. Hardware Setup Window 7. Click Auto Detect. The software should recognize the EP2C8 device, as shown in Figure A-3. 8. Click on the line with the device name to select it. Click Delete. 9. To load a new configuration, click Add File button. 10.
  • Page 57 Appendix A www.ti.com Figure A-3. EP2C8 Device Detected The software first erases the serial configuration PROM, loads it, and configures the FPGA. The progress indicator increases from 0% to 100%, indicating the configuration progress. Upon completion, LED D2 lights, indicating the FPGA is properly configured. To reprogram the FPGA directly, repeat steps nine through 12, but use a *.sof file instead of a *.jic file.

  • Page 58: Appendix B Bill Of Materials

    Appendix B www.ti.com Appendix B Bill of Materials Table B-1. TSW4100 Bill of Materials Part Reference Value Manufacturer Manufacturer's Note Part_Number A B C CCK D DCK PROBE POINT 47 µF C1 C21 C29 C39 C45 C58 Kemet T494B476M010AT C72 C73 C135 C148 C151 C153 C501 0.1 µF C3 C31 C36 C38 C41 C44...
  • Page 59 Appendix B www.ti.com Table B-1. TSW4100 Bill of Materials (continued) Part Reference Value Manufacturer Manufacturer's Note Part_Number 22 µF C110 TAJA226K010R C119 100 pF Panasonic ECJ-0EB1E101K 0.033 µF C136 0402ZC333KAT2A C137 330 pF Panasonic ECJ-0EB1E331K 4.7 µF C169 C183 TAJA475K020R 0.1 µF C176 Panasonic...
  • Page 60 Appendix B www.ti.com Table B-1. TSW4100 Bill of Materials (continued) Part Reference Value Manufacturer Manufacturer's Note Part_Number R23 R24 R30 R31 R38 R103 1.0 KΩ Panasonic ERJ-2RKF1001X R105 R110 130 Ω R25 R37 R57 R70 R156 Panasonic ERJ-2RKF1300X_DNI R178 R27 R62 R502 15.8 KΩ...
  • Page 61 TP2 TP3 TP4 TP7 TP9 TP16 BLK KEYSTONE 5001 U1 U2 U3 U4 U6 TPS76701QPWP Texas Instruments TPS76701QPWP EP2C8 Altera EP2C8F256C7N U11 U9 BGA_252_GC5016_ Texas Instruments GC5016 U5 U7 U20 TPS76733QPWP TPS76733QPWP ADS5545 Texas Instruments ADS5545IRGZT DAC5688 DAC5688RGC EPCS4 Altera...
  • Page 62 Appendix B www.ti.com Table B-1. TSW4100 Bill of Materials (continued) Part Reference Value Manufacturer Manufacturer's Note Part_Number FT245RL FTDI Chip FT245RL SN74HC241PW Texas Instruments SN74HC241PW SN74AHC541PW Texas Instruments SN74AHC541PW FT245RL FTDI Chip FT245RL VTD3-J0BC-10M VECTRON VTD3-J0BC-10M000 VTC4 VECTRON VTC4_B01C-10M00_DNI 4 - FOR THE STANDOFFS...
  • Page 63 EVALUATION BOARD/KIT IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use.
  • Page 64 Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2008, Texas Instruments Incorporated EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the input voltage range of 5 V to 6 V and the output voltage range of 0.0 V to 3.3 V.
  • Page 65 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.

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