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Texas Instruments TSW1405EVM User Manual
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Texas Instruments TSW1405EVM User Manual

Texas Instruments TSW1405EVM User Manual

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May 2012
Introduction
The TSW1405EVM Low Cost Data Capture Card from Texas Instruments (TI) assists designers in prototyping and
evaluating the performance of high-speed ADCs that feature parallel/serial LVDS outputs. The evaluation module
features a powerful LatticeECP3™-35 FPGA. The FPGA can be used as a flexible and rapid prototyping environ-
ment for digital design, interfacing directly to the LVDS output of the TI ADC under evaluation. This HDL reference
design is available for users to get started with the evaluation board and capture ADC data using the TI High Speed
Data Converter Pro software.
Figure 1. Hardware Evaluation Overview
ADS EVM
Currently, HDL reference designs targeting the LatticeECP3 device support the following TI device families:
• ADS41xx and ADS61xx single channel
• ADS62Pxx and ADS42xx dual channel
• ADS58C48 four channel
• ADS5400 dual bus
• ADS5463 single channel
• ADS5485 single channel
The HDL reference designs for these converters contain two primary modules for capturing the LVDS data from the
ADC.
• ADCIF – Contains the I/O logic and gearing functions for the LVDS pins. It also converts the double data rate
(DDR) input channel to a single data rate (SDR) parallel bus.
• DUMPMEM_TOP – Stores the channel's parallel data to internal DPRAM. The ADC data extracts a SPI control-
ler within the module. The High Speed Data Converter Pro software can import the data from this controller
through the USB port.
ADCIF module is the only design block required if the user desires to implement their own design using the
ADS41xx/ADS61xx, ADS62Pxx/ADS42xx, ADS58C48, ADS5400, ADS5463, ADS5485 with the LatticeECP3
device. The top level design instantiates the primary modules and connects them together. It also contains a LED
blinker circuit. This circuit flashes the LED when the LVDS clock output from the ADC is running and is available to
the FPGA. Figures 2 to 7 show the block diagrams for each respective ADC design.
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
TI TSW1405 High-Speed ADC
TSW1405
High Speed Data Converter Pro
1

Evaluation Board

HDL User's Guide
Reference Design RD1127
rd1127_01.2

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Summary of Contents for Texas Instruments TSW1405EVM

  • Page 1: Evaluation Board

    Reference Design RD1127 Introduction The TSW1405EVM Low Cost Data Capture Card from Texas Instruments (TI) assists designers in prototyping and evaluating the performance of high-speed ADCs that feature parallel/serial LVDS outputs. The evaluation module features a powerful LatticeECP3™-35 FPGA. The FPGA can be used as a flexible and rapid prototyping environ- ment for digital design, interfacing directly to the LVDS output of the TI ADC under evaluation.
  • Page 2 TI TSW1405 High-Speed ADC Evaluation Board HDL User’s Guide Figure 2. Single Channel ADC Block Diagram (ADS41xx/ADS61xx) TSW1405_1ch_bit_wise reset_n ADCIF DUMPMEM_TOP clk_lvds_rx_p sample 0 {[12:9], [7:4]} lvds_rx_port0 [15:0] lvds_rx_port1 port1 sample 1 iDDRx2 [15:0] DUMPMEM_DP DUMPMEM_WCTRL DUMPMEM_RCTRL spi_ss spi_clk DUMPMEM_SPI spi_miso ADC Clock Counter Figure 3.
  • Page 3 TI TSW1405 High-Speed ADC Evaluation Board HDL User’s Guide Figure 4. Four Channel ADC Block Diagram (ADS58C48) TSW1405_2ch_bit_wise reset_n ADCIF DUMPMEM_TOP clk_lvds_rx_p {[28:17], [15:10], [7:2]} lvds_rx_port0 sample 0, chan 0 lvds_rx_port1 [11:0] sample 1, chan 0 [11:0] sample 0, chan 1 [11:0] sample 1, chan 1 iDDRx2...
  • Page 4 TI TSW1405 High-Speed ADC Evaluation Board HDL User’s Guide Figure 6. Single Channel ADC Block Diagram (ADS5463) TSW1405_sample_wise reset_n ADCIF DUMPMEM_TOP clk_lvds_rx_p IDDRx2 sample 0 lvds_rx_port1 {[13:0], 4’h0} sample 0 {[13:0], 4’h0} sample 1 {[13:0], 4’h0} lvds_rx_port0 sample 1 [14:1] {[13:0], 4’h0} sample 2 {[13:0], 4’h0}...
  • Page 5 TI TSW1405 High-Speed ADC Evaluation Board HDL User’s Guide Figure 8. ADCIF Module ADCIF clk_adc_ext clk_adc inv_data dout1[15:0] inv_clk dout2[15:0] lsb_first dout3[15:0] reset_n dout4[15:0] din[28:0] dout5[15:0] cap_depth[1:0] dout6[15:0] cap_format[2:0] dout7[15:0] cap_chans[7:0] dout8[15:0] Table 1. ADCIF Module NGO I/O Descriptions TSW1405_1ch_bit_ TSW1405_2ch_bit_ TSW1405_4ch_bit_ TSW1405_sample_...
  • Page 6 TI TSW1405 High-Speed ADC Evaluation Board HDL User’s Guide Table 2. Output Control Mux Settings for Dual Channel Designs cap_chans Setting Channel(s) dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 cap_chans = 0 or 1 Channel 1 Sample 0 Sample 0 Sample 0 Sample 0 Sample 1 Sample 1 Sample 1 Sample 1 cap_chans = 2 Channel 2 Sample 0 Sample 0 Sample 0 Sample 0 Sample 1 Sample 1 Sample 1 Sample 1...
  • Page 7 TI TSW1405 High-Speed ADC Evaluation Board HDL User’s Guide Table 4. Single Channel Design Signal Names and Pinout Signal Name LatticeECP3 Pin Direction Definition reset_n Input Master Reset clk_lvds_rx_p Input Clock from TI ADC clk_lvds_rx_n lvds_rx_port0_p[4] lvds_rx_port0_n[4] lvds_rx_port0_p[5] lvds_rx_port0_n[5] lvds_rx_port0_p[6] lvds_rx_port0_n[6] lvds_rx_port0_p[7] lvds_rx_port0_n[7]...
  • Page 8 TI TSW1405 High-Speed ADC Evaluation Board HDL User’s Guide Table 5. Dual Channel Design Signal Names and Pinout Signal Name LatticeECP3 Pin Direction Definition reset_n Input Master Reset clk_lvds_rx_p Input Clock from TI ADC clk_lvds_rx_n lvds_rx_port0_p[1] lvds_rx_port0_n[1] lvds_rx_port0_p[2] lvds_rx_port0_n[2] lvds_rx_port0_p[3] lvds_rx_port0_n[3] lvds_rx_port0_p[4] lvds_rx_port0_n[4]...
  • Page 9 TI TSW1405 High-Speed ADC Evaluation Board HDL User’s Guide Table 6. Four Channel Design Signal Names and Pinout Signal Name LatticeECP3 Pin Direction Definition reset_n Input Master Reset clk_lvds_rx_p Input Clock from TI ADC clk_lvds_rx_n lvds_rx_port0_p[2] lvds_rx_port0_n[2] lvds_rx_port0_p[3] lvds_rx_port0_n[3] lvds_rx_port0_p[4] lvds_rx_port0_n[4] lvds_rx_port0_p[5] lvds_rx_port0_n[5]...
  • Page 10 TI TSW1405 High-Speed ADC Evaluation Board HDL User’s Guide Table 6. Four Channel Design Signal Names and Pinout (Continued) Signal Name LatticeECP3 Pin Direction Definition lvds_rx_port1_n[8] lvds_rx_port1_p[9] lvds_rx_port1_n[9] TI ADC Channel 1 Data lvds_rx_port1_p[10] Input (cont.) lvds_rx_port1_n[10] lvds_rx_port1_p[11] lvds_rx_port1_n[11] clk_spi Input SPI Clock spi_miso...
  • Page 11 TI TSW1405 High-Speed ADC Evaluation Board HDL User’s Guide Table 7. Dual Bus Design Signal Names and Pinout (Continued) Signal Name LatticeECP3 Pin Direction Definition lvds_rx_port1_p[3] lvds_rx_port1_n[3] lvds_rx_port1_p[4] lvds_rx_port1_n[4] lvds_rx_port1_p[5] lvds_rx_port1_n[5] lvds_rx_port1_p[6] lvds_rx_port1_n[6] lvds_rx_port1_p[7] TI ADC Channel 1 Data Input (cont.) lvds_rx_port1_n[7] lvds_rx_port1_p[8]...
  • Page 12 TI TSW1405 High-Speed ADC Evaluation Board HDL User’s Guide Table 8. Sample-Wise Design Signal Names and Pinout Signal Name LatticeECP3 Pin Direction Definition reset_n Input Master Reset clk_lvds_rx_p Input Clock from TI ADC clk_lvds_rx_n lvds_rx_port0_p[1] lvds_rx_port0_n[1] lvds_rx_port0_p[2] lvds_rx_port0_n[2] lvds_rx_port0_p[3] lvds_rx_port0_n[3] lvds_rx_port0_p[4] lvds_rx_port0_n[4] lvds_rx_port0_p[5]...

  • Page 13: Hardware Validation

    ® using Lattice Diamond 1.4 design software. ADC results were analyzed through the Texas Instruments High- Speed Data Converter Pro 1.0/1.04 GUI. The input clock frequency was set to 15 MHz at 1.5 Vpp and the ADC input was set to 100 kHz at 4.5Vpp. The supply to the ADC board was 5V or 6V depending on the board.

  • Page 14: Technical Support Assistance

    References • Texas Instruments TSW1405, High-Speed ADC LVDS Evaluation System • Texas Instruments ADS61xx, 14/12-Bit MSPS ADCs With DDR LVDS and Parallel CMOS Outputs Data Sheet • Texas Instruments ADS4249, Dual-Channel, 14-Bit, 250-MSPS Ultralow-Power ADC Data Sheet • Texas Instruments ADS58C48, Quad Channel IF Receiver with SNR Boost Data Sheet •...