Lpc; Serial Bus - Advantech SOM-5993 User Manual

PCIe x8, [7:0]
® ®
Intel Xeon Processor D natively integrates 1 x PCI express x8 lanes and up to 4 x
devices at up to Gen3 speeds (8.0 GT/s).
SOM-5993 supports 1 PCIe x4 and 2 x2 in default, and is configurable to 4 x2, 1 x4
and 2 x2, 2 x2 and 1 x4 or 2 x4, 1 x8.
Type 7
Default
Option 1
Option 2
Config.
Option 3
Option 4
Option 5
PCIe x8, [15:8]
® ®
Intel Xeon Processor D natively integrates 1 x PCIe x8 lanes and up to 4 x devices
at up to Gen3 speed (8.0 GT/s).
SOM-5993 supports 1 x PCIe x8 by default, and is configurable to 4 x2, 1 x4 and 2
x2, 2 x2 and 1 x4 or 2 x4.
Type 7
Default
Option 1
Option 2
Config
Option 3
Option 4
Option 5
1.3.7

LPC

This solution supports Low Pin Count (LPC) 1.1 specifications, without DMA or bus
mastering. This allows it to connect super I/O, embedded controllers, or TPM. LPC
clock is 25MHz.
1.3.8

Serial Bus

1.3.8.1 SMBus
Support SMBus 2.0 specifications with alert pins.
1.3.8.2 I2C Bus
Supports I2C bus 8-bit and 10-bit address modes, at both 100KHz and 400KHz.
SOM-5993 User Manual
Row A,B
P0 P1 P2
X4
X2 X2
X4
X2 X2
X4
P8 P9 P10
X2 X2
X4
X2 X2
X4
8
P3 P4 P5
X2
X2
X2
X4
X4
X8
Row A,B
P11 P12 P13
X8
X2
X2
X4
X4
X8
Row C,D
P6 P7
X2
X2
X2
P14 P15
X2
X2