Supermicro X13SAV-PS User Manual page 71

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64-bit
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EIST Technology
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CPU C3 state
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CPU C6 state
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CPU C7 state
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CPU C8 state
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CPU C9 state
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CPU C10 state
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Performance L1 Data Cache
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Performance L1 Instruction Cache
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Performance L2 Cache
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Performance L3 Cache
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Efficient L1 Data Cache
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Efficient L1 Instruction Cache
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Efficient L2 Cache
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Efficient L3 Cache
C6DRAM
Use this feature to enable or disable the moving of DRAM contents to PRM memory when
the CPU is in the C6 state. The options are Disabled and Enabled.
Hardware Prefetcher (Available when supported by the CPU)
If set to Enable, the hardware prefetcher will prefetch streams of data and instructions from
the main memory to the L2 cache to improve CPU performance. The options are Disabled
and Enabled.
Adjacent Cache Prefetch (Available when supported by the CPU)
The CPU prefetches the cache line for 64 bytes if this feature is set to Disabled. The CPU
prefetches both cache lines for 128 bytes as comprised if this feature is set to Enable. The
options are Disabled and Enabled.
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Chapter 4: UEFI BIOS