Supported Dram; Serial Port S1 Multiplexer Control; Table 13: Pci Interrupt Map - Broadcom BCM91250A User Manual

User Manual
05/18/04
BCM1250 PCI INTA = PCI connector (J15) INTA
BCM1250 PCI INTB = PCI connector (J15) INTB
BCM1250 PCI INTC = PCI connector (J15) INTC
BCM1250 PCI INTD = PCI connector (J15) INTD
BCM1250 PCI INTA = PCI connector (J16) INTD
BCM1250 PCI INTB = PCI connector (J16) INTA
BCM1250 PCI INTC = PCI connector (J16) INTB
BCM1250 PCI INTD = PCI connector (J16) INTC
BCM1250 PCI INTC = Firelink 82C861 INTA
SiPackets SP1011 INTA = PCI connector (J26) INTA
SiPackets SP1011 INTB = PCI connector (J26) INTB
SiPackets SP1011 INTC = PCI connector (J26) INTC
SiPackets SP1011 INTD = PCI connector (J26) INTD
SiPackets SP1011 INTA = PCI connector (J53) INTD
SiPackets SP1011 INTB = PCI connector (J53) INTA
SiPackets SP1011 INTC = PCI connector (J53) INTB
SiPackets SP1011 INTD = PCI connector (J53) INTC
S DRAM
UPPORTED
Although this board ships with two 128MB DDR SDRAM DIMMs, it can support other DIMMs as well. This
includes standard PC2100 and PC2700 DDR SDRAM DIMMs, either buffered or unbuffered and with or
without ECC.
The two provided DIMMs are placed in MC channel 0 slot 0 and MC channel 1 slot 0 by default. This provides
the best memory utilization for two DIMMs because channel interleaving can be used.
Other available configurations for installing more or different DIMMs are as follows:
• Two identical DIMMs can be inserted in slot 1 of both channels to provide the best possible memory
utilization.
• If you choose to put two DIMMs on a single channel, then the DIMM timing/characteristics must be
identical. The firmware then uses chip select interleaving when configuring the memory controller.
• Finally, populating all four slots with identical DIMMs provides the best possible memory utilization for this
board. This will allow both chip select and channel interleaving to be configured.
S P S1 M
ERIAL ORT
This serial port can be configured as either a standard asynchronous UART with an RS232 interface or a
synchronous Crystal CS4297A audio codec. The mux control for this port is controlled by setting the
BCM1250's E2_GENO signal. When that signal is low, the UART is active and when it is high the audio codec
is active.
Document 91250A-UM100-R

Table 13: PCI Interrupt Map

Interrupt Map
C
ULTIPLEXER ONTROL
B roadc om C or por ati on
BCM91250A
Description
32-bit PCI connector (J15)
32-bit PCI connector (J16)
Firelink 82C861 PCI to USB bridge
64-bit PCI connector (J26)
64-bit PCI connector (J53)

Supported DRAM

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