Acceptable Pll Settings; Supported Dram; Table 7: Acceptable Pll Settings - Broadcom BCM91125PCIX User Manual

BCM91125PCIX
A PLL S
CCEPTABLE
Table 7 shows acceptable PLL settings. Adjusting dip switch SW11 changes the multiplier of the CLK100.
Note: The default PLL settings are set according to the speed bin of the BCM1125H part. That
setting is the maximum clock speed that the chip can attain without failure.
SW11 dip[4:8] settings
off,off,on,off,off
off,off,on,off,on
off,off,on,on,off
off,off,on,on,on
on,off,off,off,off
on,off,off,off,on
on,off,off,on,off
on,off,off,on,on
on,off,on,off,off
S DRAM
UPPORTED
Although this board ships with two 256MB DDR SDRAM DIMMs, it can support other DIMMs as well. This
includes standard PC2100 and PC2700 DDR SDRAM DIMMs, either buffered or unbuffered and with or
without ECC.
Note: Both DIMMs must operate at the same speed since there is only a single memory channel.
Page 18

Acceptable PLL Settings

ETTINGS

Table 7: Acceptable PLL Settings

pll_div[4:0]
01100
01101
01110
01111
11000
11001
11010
11011
11100
B roadc om C or por ati on
User Manual
CLK100 MHz
CPU clock (MHz)
Multiplier
6.0x
6.5x
7.0x
7.5x
8.0x
8.5x
9.0x
9.5x
10.0x
Document 91125PCIX-UM100-R
07/02/04
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