Acceptable Pll Settings; Acceptable I/O Bridge Settings; Table 8: Acceptable Pll Settings; Table 9: Acceptable I/O Bridge Settings - Broadcom BCM91250A User Manual

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Table Of Contents

Table of Contents

User Manual

05/18/04

PLL S

CCEPTABLE

Table 8

shows acceptable PLL settings. These settings require a combination of a jumper (J3) and a switch

(SW2).

Note: The default PLL settings are set according to the speed bin of the BCM1250 part. That

setting is the maximum clock speed that the chip can attain without failure.

J3 setting

pll_div[3]

open = 1

1-2 = 0

open

I/O B

CCEPTABLE

The BCM1250 contains two bridges which isolate many of the chip's SOC components from the core, L2

cache, and other components. More details about these bridges can be found in the user manual for the

specific chip. The clocking for these bridges is determined by dividing the CPU clock. The allowable divide

ratios for a given bridge at a certain CPU frequency are provided below.

Document

91250A-UM100-R

ETTINGS

Table 8: Acceptable PLL Settings

SW2 setting

pll_div[4,2:0]

0x4

0x5

0x6

0x7

0x8

0x9

0xA

0xB

0xC

RIDGE

ETTINGS

Table 9: Acceptable I/O Bridge Settings

CPU clock (MHz)

IOB0 divide ratio

600-650

3 or 4

700-1000

3 or 4

B roadc om C or por ati on

CLK100 MHz

pll_div[4:0]

Multipler

01100

01101

6.5x

01110

01111

7.5x

11000

11001

8.5x

11010

11011

9.5x

11100

10x

IOB1 divide ratio

2 or 3