System Registers - Advantech EH-8100 Reference Manual

7 6
IM_C3R IM_C2R
Bit Symbol
D0 IM_C0 Channel 0 Socket Interrupt Enable.
D1 IM_C1 Channel 1 Socket Interrupt Enable.
D2 IM_C2 Channel 2 Socket Interrupt Enable.
D3 IM_C3 Channel 3 Socket Interrupt Enable.
D4 IM_C0R Channel 0 Socket data receipt Interrupt Enable.
D5 IM_C1R Channel 1 Socket data receipt Interrupt Enable.
D6 IM_C2R Channel 2 Socket data receipt Interrupt Enable.
D7 IM_C3R Channel 3 Socket data receipt Interrupt Enable.

2. System Registers

GAR (Gateway Address Register) [R/W, 0x80 – 0x83]
This register sets up the default gateway address to be used in the system, which is required to be set
IP address before executing Sys_Init command.
SMR (Subnet Mask Register) [R/W, 0x84 – 0x87]
This register sets up the subnet mask to be used in the system, which is required to be set up before
executing Sys_Init command.
SHAR (Source Hardware Address Register) [R/W, 0x88 – 0x8D]
This register sets up the HA to be used in the system, which is required to be set up before executing
Sys_Init command.
SIPR (Source IP Address Register) [R/W, 0x8E – 0x91]
This register sets up the IP to be used in the system, which is required to be set up before executing
Sys_Init command.
IRTR (Initial Retry Time-value Register) [R/W, 0x92 – 0x93]
This register sets up the timer value for initial re-transmission when using the TCP, and timer value
1 is equivalent to 100us.
Value Timer (ms)
0x03E8 100
0x07D0 200
0x0FA0 400
RCR (Retry Count Register) [R/W, 0x94]
This register assigns the number of retry when re-transmission occurs, and timeout interrupt occurs
when retransmission exceeds the number of retry.
RMSR (Rx data Memory Size Register) [R/W, 0x95]
This register allocates 8KB of received memory for each channel.
CH3
S1 S0
5 4
IM_C1R IM_C0R IM_C3
CH2
S1 S0
- 9 -
3 2 1
IM_C2 IM_C1
Description
CH1
S1 S0 S1
0
IM_C0
CH0
S0