Advantech EH-8100 Reference Manual
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Advantech EH-8100 Reference Manual

Ethernet & tcp/ip protocols stack
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EH-8100
Ethernet & TCP/IP
Protocols Stack
Reference Guide
- 1 -

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Summary of Contents for Advantech EH-8100

  • Page 1 EH-8100 Ethernet & TCP/IP Protocols Stack Reference Guide - 1 -...

  • Page 2: Table Of Contents

    Table of Contents Description …………………………………………………………… Features ………………………………………………………………. Hardware Ethernet&TCP/IP Protocols stack Registers Map … Register Definitions …………………………………………………. Control Registers ………………………………………………. System Registers ………………………………………………. Pointer Registers ………………………………………………. Channel Registers ……………………………………………… 12 Internal Memory and Registers …………………………………… Description of Functions …………………………………………… 16 Initialization ………………………………………………………...

  • Page 3: Description

    ” Description The Ethernet interface of EH-8100-Lx is an LSI of hardware protocol stack that provides an easy, low-cost solution for high-speed Internet connectivity for digital devices by allowing simple installation of TCP/IP stack in the hardware. The Ethernet interface of EH-8100-Lx offers system designers a quick, easy way to add Ethernet networking functionality to any product.

  • Page 4: Hardware Ethernet&Tcp/Ip Protocols Stack Registers Map

    Table1. Hardware Ethernet & TCP/IP Protocols stack Registers Map ( Register Base Address is 0x8000 ) Address Register Bit Definitions 0x00 C0_CR S/W Reset Recv Send Close Listen Connect Sock_Init Sys_Init Memory Test Recv Send Close Listen Connect Sock_Init 0x01 C1_CR 0x02 C2_CR...
  • Page 5 Initial Retry Time-value Register 0x92 – 0x93 IRTR 0x94 0x95 RMSR Rx data Memory Size Register Tx data Memory Size Register 0x96 TMSR 0x97 – 0x9F Reserved Channel 0 Socket Status Register 0xA0 C0_SSR NDAck SWS/P Protocol Protocol Protocol 0xA1 C0_SOPR Broadcast/ERR NDTimeout/B 0xA2 –...

  • Page 6: Register Definitions

    Register Definitions. Register sets are categorized into (i) control registers related to command, status and interrupt, (ii) system registers for gateway address, subnet mask, source IP, source HA (Hardware Address) and timeout value, (iii) pointer registers for managing to send, receive data, and (iv) channel registers that control operation of each channel.
  • Page 7 Command to stand by for connection when Channel 1 socket acts in server Listen mode Close Command to terminate connection and close Channel 1 socket Send Command to transmit Channel 1 socket data Recv Command to receive Channel 1 socket data Memory Test Command to set memory test mode C2_CR, C3_CR (Channel 2, 3 Command Register) [R/W, 0x02, 0x03] The register commands each Channel 2, 3 sockets to initialize, connect, close, transmit and receive...
  • Page 8 C1_ISR, C2_ISR, C3_ISR (Channel 1, 2, 3 Interrupt Status Register) [R, 0x05, 0x06, 0x07] This register notifies the outcome of the command of each Channel 1, 2 and 3. This register becomes cleared as 0x00 by read operation. Established notifies the completion of a connection executed by connection set-up command (Connect, Listen).

  • Page 9: System Registers

    IM_C3R IM_C2R IM_C1R IM_C0R IM_C3 IM_C2 IM_C1 IM_C0 Symbol Description IM_C0 Channel 0 Socket Interrupt Enable. IM_C1 Channel 1 Socket Interrupt Enable. IM_C2 Channel 2 Socket Interrupt Enable. IM_C3 Channel 3 Socket Interrupt Enable. IM_C0R Channel 0 Socket data receipt Interrupt Enable. IM_C1R Channel 1 Socket data receipt Interrupt Enable.

  • Page 10: Pointer Registers

    Tx_CLK * 4 is required before reading the corresponding pointer register. (Access by EH-8100-Lx MCU I/F is based on 1Byte unit, but the pointer register is comprised of 4Bytes. Therefore, shadow register is used in order for MCU to properly read 4Byte pointer.) To write, no access to the shadow register or time delay is necessary.
  • Page 11 C2 : 0x28 – 0x2B, C3 : 0x34 – 0x37] Included in each channel, this register displays the data end pointer when receiving data. The register is managed internally by the Ethernet I/F of EH-8100-Lx and increases according to the size of the data received.

  • Page 12: Channel Registers

    Standing by for reply after transmitting ARP request packet to the destination for UDP transmission 0X12 SOCK_UDP_DATA Data transmission in progress in UDP or RAW mode 0X13 SOCK_RAW_INIT The Ethernet I/F of EH-8100-Lx initialized in MAC layer RAW mode - 12 -...
  • Page 13 In active mode, IP address needs to be set before executing the Connect command. In passive mode, EH-8100-Lx sets up the connection and then updates as peer IP internally. DPR (Destination Port Register) [R/W, C0 : 0xAC – 0xAD, C1 : 0xC4 – 0xC5, C2 : 0xDC –...
  • Page 14 C2 : 0xDE – 0xDF, C3 : 0xF6 – 0xF7] This register sets the Source Port number for each channel when using TCP or UDP mode, and the set-up needs to be made before executing the Sock_Init Command. IPR (IP Protocol Register) [R/W, C0 : 0xB0, C1 : 0xC8, C2 : 0xE0, C3 : 0xF8] This IP Protocol Register is used to be set up at the Protocol Field of IP Header when executing the IP Layer RAW Mode, and the set-up needs to be made before executing the Sock_Init Command.

  • Page 15: Internal Memory And Registers

    Reserved 8200h Ethernet Control Reg. 8000h The Ethernet I/F of EH-8100-Lx internal register and memory are comprised of 512 byte Control Registers and 16KB data buffer as displayed in the diagram above. 0x8000 ~ 0x80FF : Space for Control Registers...

  • Page 16: Description Of Functions

    Description of Functions 1. Initialization In order to use the Ethernet I/F of EH-8100-Lx, the basic registers that are required to run the Ethernet I/F of EH-8100-Lx need to be set up. The basic registers include GAR (Gateway Address Register), SMR (Subnet Mask Register), SHAR (Source Hardware Address Register), and SIPR (Source IP Address Register).
  • Page 17 CLOSED state. d. SYNSENT state: In this state, the Ethernet I/F of EH-8100-Lx transmits SYN packet and stands by to receive SYN,ACK packet from the peer. In case appropriate SYN,ACK packet is received, the Ethernet I/F of EH-8100-Lx transmits ACK packet and completes the connection set-up to become changed to ESTABLISHED state.
  • Page 18 CLOSED state. FIN_WAIT2 state: stands by for FIN from the peer. In this state, the Ethernet I/F of EH-8100-Lx does not receive data from the peer, and if data is received, connection set-up is immediately terminated through RST.
  • Page 19 8KB by using RMSR (Rx data Memory Size Register) and TMSR (Tx data Memory Size Register). TCP Transmission Memory Size Set-up The Ethernet I/F of EH-8100-Lx transmission memory is comprised of 8KB in total, and the size can be assigned for each channel through TMSR register. An example of TMSR and each memory size is illustrated in the diagram below.
  • Page 20 Above diagram illustrates the change in Cx_TW_PR and Cx_TA_PR when actual data transmission is made after 2KB of transmission memory is set at CH0. TCP Reception Memory Size Set-up Receiving memory of the Ethernet I/F of EH-8100-Lx has the same structure of the transmission - 20 -...
  • Page 21 Reception Memory Allocation TCP Data Reception Process TCP data reception by the Ethernet I/F of EH-8100-Lx is illustrated in the above diagram. In the Ethernet I/F of EH-8100-Lx, when data is received from the peer, the data is recorded as reception...

  • Page 22: Udp Protocol

    2KB of reception memory is set at CH0. TCP Retry Time Adjustment The Ethernet I/F of EH-8100-Lx uses IRTR (Initial Retry Time-value Register) and RCR (Retry Count Register) to adjust the timer to be used in re-transmission of TCP.
  • Page 23 UDP transmission is activated similarly to TCP. All data received at its port can be received, and MCU needs to analyze the header information of the data to verify transmitting IP and port to confirm the corresponding data before processing. Set-up of transmission and reception memory size is identical to TCP.
  • Page 24 UDP Data Reception UDP reception is similar to TCP reception. The difference is that the header information for UDP processing is included in the received data in addition to the data. The header is structured as below. TLEN SPort UDP data The header is comprised of (1) TLEN Field displaying the size of 2Byte Header + data, (2) 4Byte SIP displaying the sender IP that transmitted UDP data, and (3) SPort displaying the sender Port.

  • Page 25: Ip Layer Raw Mode

    IPL_RAW Mode Initialization Process In order to use the Ethernet I/F of EH-8100-Lx IPL_RAW Mode, the protocol value of the IP Layer to be used (e.g., 0x01 in case of ICMP) needs to be set as Cx_IPR (IP Protocol Register of Channel...
  • Page 26 2KB of transmission memory is set at CH0. IPL_RAW Mode Data Reception Reception in the Ethernet I/F of EH-8100-Lx IPL_RAW Mode is similar to UDP reception. As in UDP, header information is included in the received data in addition to the data, and the header is structure as below.

  • Page 27: Mac Layer Raw Mode

    For systems using more than 4 channels simultaneously, the Ethernet I/F of EH-8100-Lx uses this mode and S/W TCP/IP can be processed in the higher drive. If MAC Layer RAW Mode is used, the Ethernet I/F of EH-8100-Lx uses Channel 0 only and other channels are ignored.
  • Page 28 C0_RR_PR are equally initialized as 0x00000200. MACL_RAW Mode Data Reception In the Ethernet I/F of EH-8100-Lx MACL_RAW Mode, the reception of the set packets are made according to the receive options as set at C0_SOPR. As in UDP, header information is included in the received data in addition to the data, and the header is structure as below.
  • Page 29 Meaning Destination H/W Address of the received packet is identical to SHAR (Source H/W Address Register) x Reception of Broadcasting Packet x Reception of Packet with Error As in UDP, the reception module uses C0_RW_PR and C0_RR_PR to process the received data. The process is identical to UDP received data process.

  • Page 30: Appendix A. Programming Guide

    2. Notes when setting “MSS maximum value” Maximum MSS value of the Ethernet I/F of EH-8100-Lx is limited to 1460 in UDP or IP Raw mode. Therefore, do not set an MSS value greater than 1460 in UDP or IP Raw mode.

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