Toshiba TC9314F Manual page 6

Pin No. Symbol
Test mode control
66 TEST
input
Hold mode control
67 HOLD
input
68 IF /IN1 IF signal input
IN1
/input port
69 IF /IN2
IN2
70 DO1 Phase comparator
output
71 DO2/OT2 Phase comparator
output/output port
Pin Name
Input pin for controlling test mode.
When the pin is high, test mode; when low, normal
operation.
Normally used low or in the NC state. (pull-down
resistance built in)
Input pin used to request/cancel a hold state.
Normally used for the radio mode select signal
input or for the battery detection signal input.
Hold states can be either clock stop mode (crystal
oscillation stopped) or wait mode (CPU stopped).
The mode is set by a CKSTP or WAIT instruction.
When CKSTP instruction is executed, the hold
state request/cancel differs depending on the
internal MODE bit. When the MODE bit is 0
(MODE-0), executing the CKSTP instruction while
the HOLD pin is low stops the clock generator
and the CPU, and enters memory backup state.
When the MODE bit is 1 (MODE-1), executing the
CKSTP instruction regardless of whether the
HOLD pin is high or low enters memory backup
state. This state is canceled in MODE-0 when the
HOLD pin changes to high; in MODE-1, when
the input at the HOLD pin changes.
When a WAIT instruction is executed, the state is
cancelled by changes in inputs at this pin.
During memory backup, current consumption is
reduced (to 1 A or less) and all output pins
(display outputs, output ports, etc.) automatically
are set to low.
IF signal input pin for the IF counter; counts the IF
signals for the FM and AM bands and detects
autostop.
Input frequency is 0.3~12 MHz (0.2 V
built-in input amplifier operates at small amplitude
withcapacitors connected.
The IF counter is a 20 bit counter with gate time
selectable to 1, 4, 16 or 64 ms, allowing 20 bits of
data to be loaded to memory directly.
This input pin can be programmed as an input port
(IN port).
When set to IN port, input is CMOS level.
PLL phase comparator output pin.
Tri-state output. When the divider output of the
programmable counter is higher than the
reference frequency, high level is output; when
lower, low level is output. When they accord, the
output is at high impedance.
DO1 and DO2 are parallel outputs, allowing
optimized design of filter constants for both the
FM and AM bands.
The DO2 pin can also be set to high impedance or
as an output port (OT2) by program. Thus these
two pins can be used to improve lockup time, or to
provide effective use of pins as output ports.
Function and Operation
min). The
p-p
6
TC9314F
Remarks
2003-07-03