VIA Technologies P4XB-S User Manual page 51

receive more data. Setting options: Enabled, Disabled.
PCI Master 0 WS Write
When Enabled, writes to the PCI bus are executed with zero wait state.
Setting options: Enabled, Disabled.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transaction cycles. Select Enabled to support compliance with PCI speci-
fication version 2.1. Setting options: Enabled, Disabled.
System BIOS Cacheable
When enabled, this setting sets BIOS write-through at DRAM segment F000
and makes the BIOS execution speed faster. Setting options: Enabled, Disabled.
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BIOS Setup