VIA Technologies P4XB-S User Manual page 48

Chapter 3
the contents of the SPD (Serial Presence Detect) EPROM on the DRAM
module. Selecting Yes makes SDRAM Cycle Length and Bank Interleave
automatically determined by BIOS according to the configurations on the
SPD. Setting options: Yes, No.
DRAM Frequency (MHz)
The chipset supports synchronous and asynchronous mode between
host clock and DRAM clock frequency. Available settings are:
Auto:
Host CLK:
HCLK+33: The DRAM clock will be equal to the Host clock
SDRAM CAS Latency
The field controls the CAS latency, which determines the timing delay
before SDRAM starts a read command after receiving it. Setting options:
2, 2.5 (clock cycles), Auto. 2 increases system performance while 3 pro-
vides more stable system performance.
Bank Interleave
This setting determines the bank interleave for the installed SDRAM.
Setting options: Disabled, Auto.
Row Precharge
This setting allows you to select the number of DRAM clocks allocated
for the Row Address Strobe (RAS#) signal to accumulate its charge be-
fore the DRAM is refreshed. If insufficient time is allowed, refresh may be
incomplete and data lost. The lower the timing numbers, the faster the
memory performance. Setting options: 3T, 2T, Auto.
RAS Pulse
This setting allows you to select the number of DRAM clock cycles
allotted for the RAS pulse width, according to DRAM specifications.The
lower the timing numbers, the faster the memory performance. Setting
options: 6T, 5T, Auto.
DRAM clock frequency is automatically
determined.
The DRAM clock will be equal to the Host clock.
plus 33MHz. For example, if the Host clock is
100MHz, the DRAM clock will 133MHz.
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