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Register Name:
Register Description:
Register Address:
Bit #
7
Name
BBC7
Default
0
Bit #
15
Name
BBC15
Default
0
Register Name:
Register Description:
Register Address:
Bit #
7
Name
BBC23
Default
0
Bit #
15
Name
BBC31
Default
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 31: BERT 32-Bit Bit Counter (BBC0 to BBC31). This 32-bit counter will increment for each data bit
(i.e., clock received). This counter is not disabled when the receive BERT loses synchronization. This counter can
be cleared by toggling the LC control bit in BERTC0. This counter saturates and will not rollover. Upon saturation,
the BBCO status bit in the BERTEC0 register will be set. This error counter starts counting when the BERT goes
into receive synchronization (RLOS = 0 or SYNC = 1) and it will not stop counting when the BERT loses
synchronization. It is recommended that the host toggle the LC bit in BERTC0 register once the BERT has
synchronized and then toggle the LC bit again when the error-checking period is complete. If the device loses
synchronization during this period, then the counting results are suspect.
BERTBC0
BERT 32-Bit Bit Counter (lower word)
78h
6
5
BBC6
BBC5
0
0
14
13
BBC14
BBC13
0
0
BERTBC1
BERT 32-Bit Bit Counter (upper word)
7Ah
6
5
BBC22
BBC21
0
0
14
13
BBC30
BBC29
0
0
4
3
BBC4
BBC3
0
0
12
11
BBC12
BBC11
0
0
4
3
BBC20
BBC19
0
0
12
11
BBC28
BBC27
0
0
84 of 133
2
1
BBC2
BBC1
0
0
10
9
BBC10
BBC9
0
0
2
1
BBC18
BBC17
0
0
10
9
BBC26
BBC25
0
0
DS3112
0
BBC0
0
8
BBC8
0
0
BBC16
0
8
BBC24
0
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