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Register Name:
Register Description:
Register Address:
Bit #
7
Name
PBS
Default
0
Bit #
15
Name
IESYNC
Default
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0: Force Resynchronization (RESYNC). A low to high transition will force the receive BERT synchronizer
to resynchronize to the incoming data stream. This bit should be toggled from low to high whenever the host
wishes to acquire synchronization on a new pattern. Must be cleared and set again for a subsequent
resynchronization.
Bit 1: Load Bit and Error Counters (LC). A low to high transition latches the current bit and error counts into
the host accessible registers BERTBC and BERTEC and clears the internal count. This bit should be toggled from
low to high whenever the host wishes to begin a new acquisition period. Must be cleared and set again for a
subsequent loads.
Bits 2 to 4: Pattern Select Bits 0 (PS0 to PS2).
If PBS = 0:
000 = Pseudorandom Pattern 2
001 = Pseudorandom Pattern 2
010 = Pseudorandom Pattern 2
011 = Pseudorandom Pattern QRSS (2E20 - 1 with a one forced if the next 14 positions are zero)
100 = Repetitive Pattern
101 = Alternating Word Pattern
110 = Illegal State
111 = Illegal State
If PBS = 1:
000 = Psuedorandom Pattern 2
001 = Pseudorandom Pattern 2
010 = Pseudorandom Pattern 2
011 = Illegal State
10X = Illegal State (X = 0 or 1)
11X = lllegal State (X = 0 or 1)
Bit 5: Receive Invert Data Enable (RINV).
0 = do not invert the incoming data stream
1 = invert the incoming data stream
Bit 6: Transmit Invert Data Enable (TINV).
0 = do not invert the outgoing data stream
1 = invert the outgoing data stream
Bit 7: Pattern Bank Select (PBS)
0 = PS[2:0] select a pattern from Pattern Bank 0
1 = PS[2:0] select a pattern from Pattern Bank 1
BERTC0
BERT Control Register 0
70h
6
5
TINV
RINV
0
0
14
13
IEBED
IEOF
0
0
7
- 1 (ANSI T1.403-1999 Annex B)
11
- 1 (ITU O.153)
15
- 1 (ITU O.151)
9
- 1
20
- 1 (non-QRSS)
23
- 1 (ITU O.151)
4
3
PS2
PS1
0
0
12
11
n/a
RPL3
-
0
80 of 133
2
1
PS0
LC
0
0
10
9
RPL2
RPL1
0
0
DS3112
0
RESYNC
0
8
RPL0
0
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