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Bit 7: T3/E3 Diagnostic Loopback Enable (DLB). See
loopback.
0 = disable loopback
1 = enable loopback
Bit 8: E3 Code Violation Enable (E3CVE). This bit is ignored in the T3 mode. This bit is used in the E3 mode to
configure the BiPolar Violation Count Register (BPVCR) to count either BiPolar Violations (BPV) or Code
Violations (CV). A BPV is defined as consecutive pulses (or marks) of the same polarity that are not part of a
HDB3 codeword. A CV is defined in ITU O.161 as consecutive BPVs of the same polarity.
0 = count BPV
1 = count CV
Bits 9 and 10: T3/E3 Frame Error Counting Control Bits 0 and 1 (FECC0 and FECC1).
FECC1
FECC0
0
0
0
1
1
0
1
1
Bit 11: Error Counting Control (ECC). This bit is used to control whether the device will increment the error
counters during Loss Of Frame (LOF) conditions. It only affects the error counters that count errors that are based
on framed information and these include the following:
Frame Error Counter (when it is configured to count frame errors, not LOF occurrences)
T3 Parity Bit Error Counter
T3 C-Bit Parity Error Counter
T3 Far End Block Error or E3 RAI Counter
When this bit is set low, these error counters will not be allowed to increment during LOF conditions. When this bit
is set high, these error counters will be allowed to increment during LOF conditions.
0 = stop the FECR/PCR/CPCR/FEBECR error counters from incrementing during LOF
1 = allow the FECR/PCR/CPCR/FEBECR error counters to increment during LOF
Bit 12: Automatic FEBE Defeat (AFEBED). This bit is ignored in the E3 mode and in the T3 mode when the
device is not configured in the C-Bit Parity Mode. When this bit is low, the device will automatically insert the
FEBE codes into the transmitted data stream by setting all three C bits in Subframe 4 to zero.
0 = automatically insert FEBE codes in the transmit data stream based on detected errors
1 = use the TFEBE control to determine the state of the FEBE codes
Bit 13: Transmit FEBE Setting (TFEBE). This bit is only active when AFEBED is active (i.e., AFEBED = 1).
When this bit is low, the device will force the FEBE code to 111 continuously. When this bit is set high, the device
will force the FEBE code to 000 continuously.
0 = force FEBE to 111 (null state)
1 = force FEBE to 000 (active state)
Bit 14: T3/E3 Payload Loopback Enable (PLB). See
loopback.
0 = disable loopback
1 = enable loopback
FRAME ERROR COUNT REGISTER (FECR) CONFIGURATION
T3 Mode: Count Loss Of Frame (LOF) Occurrences
E3 Mode: Count Loss Of Frame (LOF) Occurrences
T3 Mode: Count Both F Bit and M Bit Errors
E3 Mode: Count Bit Errors in the FAS Word
T3 Mode: Count Only F Bit Errors
E3 Mode: Count Word Errors in the FAS Word
T3 Mode: Count Only M Bit Errors
E3 Mode: Illegal State
Figure 1-1
and
Figure 1-2
Figure 1-1
and
Figure 1-2
50 of 133
DS3112
for a visual description of this
for a visual description of this
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