Dallas Semiconductor MAXIM DS3112 Manual page 46

Register Name:
Register Description:
Register Address:
Bit # 7
Name —
Default —
Bit # 15
Name —
Default
—
Bit 0: One-Second Timer Boundary Occurrence (OST).
0 = interrupt masked
1 = interrupt unmasked
Bit 1: Counter Overflow Event (COVF).
0 = interrupt masked
1 = interrupt unmasked
Bit 2: Change in BERT Status (BERT).
0 = interrupt masked
1 = interrupt unmasked
Bit 3: Change in HDLC Status (HDLC).
0 = interrupt masked
1 = interrupt unmasked
Bit 4: Change in FEAC Status (FEAC).
0 = interrupt masked
1 = interrupt unmasked
Bit 5: Change in T2/E2 LOF or AIS Status (T2E2SR1).
0 = interrupt masked
1 = interrupt unmasked
Bit 6: Change in T2/E2 RAI Status (T2E2SR2).
0 = interrupt masked
1 = interrupt unmasked
Bit 8: T1 Loopback Detected (T1LB).
0 = interrupt masked
1 = interrupt unmasked
Bit 9: Change in T3/E3 Framer Status (T3E3SR).
0 = interrupt masked
1 = interrupt unmasked
Bit 10: Loss Of Transmit Clock (LOTC).
0 = interrupt masked
1 = interrupt unmasked
Bit 11: Loss Of Receive Clock (LORC).
0 = interrupt masked
1 = interrupt unmasked
IMSR
Interrupt Mask for Master Status Register
0Ah
6 5
T2E2SR2 T2E2SR1
0 0
14 13
— —
— —
4 3
FEAC HDLC
0 0
12 11
— LORC
— 0
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2 1
BERT COVF
0 0
10 9
LOTC T3E3SR
0 0
DS3112
0
OST
0
8
T1LB
0