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Bits 5 and 6: Frame Bit Error Insert Control Bits 0 and 1 (FBEIC0 and FBEIC1).
FBEIC1
FBEIC0
0
0
0
1
1
0
1
1
Bit 7: Manual Error Insert Mode Select (MEIMS). When this bit is set low, the device will insert errors on each
0 to 1 transition of the BPVI, EXZI, T3PBEI, T3CPBEI, or FBEI control bits. When this bit is set high, the device
will insert errors on each 0 to 1 transition of the FTMEI input signal. The appropriate BPVI, EXZI, T3PBEI,
T3CPBEI, or FBEI control bit must be set to one for this to occur. If all of the BPVI, EXZI, T3PBEI, T3CPBEI,
and FBEI control bits are set to zero, no errors are inserted.
0 = use zero to one transition on the BPVI, EXZI, T3PBEI, T3CPBEI, or FBEI control bits to insert errors
1 = use zero to one transition on the FTMEI input signal to insert errors
TYPE OF FRAMING BIT ERROR INSERTED
T3 Mode: A single F-bit error
E3 Mode: A single FAS word of 1111000000 is generated instead of the normal FAS
word, which is 1111010000 (i.e., only 1 bit inverted)
T3 Mode: A single M-bit error
E3 Mode: A single FAS word of 0000101111 is generated instead of the normal FAS
word, which is 1111010000 (i.e., all FAS bits are inverted)
T3 Mode: Four consecutive F-bit errors (causes the far end to lose synchronization)
E3 Mode: Four consecutive FAS words of 1111000000 are generated instead of the
normal FAS word, which is 1111010000 (i.e., only 1 bit inverted; causes the far end
to lose synchronization)
T3 Mode: Three consecutive M-bit errors (causes the far end to lose synchronization)
E3 Mode: Four consecutive FAS words of 0000101111 are generated instead of the
normal FAS word, which is 1111010000 (i.e., all FAS bits are inverted; causes the far
end to lose synchronization)
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DS3112
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