A/D Data & Channel Registers (Cio-Das1600/12) - Measurement Computing CIO-DAS1601/12 Manual

ADDRESS
BASE
BASE + 1
BASE + 2
BASE + 3
BASE + 4
BASE + 5
BASE + 6
BASE + 7
BASE + 8
BASE + 9
BASE + Ah
BASE + Bh
BASE + Ch
BASE + Dh
BASE + Eh
BASE + Fh
BASE + 400h
BASE + 401h
BASE + 402h
BASE + 403h
BASE + 404h
BASE + 405h
BASE + 406h
BASE + 407h
6.1.1 A/D DATA & CHANNEL REGISTERS (CIO-DAS1600/12)
BASE ADDRESS +0
7 6
A/D 3 A/D 2
A read/write register.
READ
On read, it contains two types of data. The least significant four digits of the analog input data and the
channel number from which the current data was taken.
These four bits of analog input data must be combined with the eight bits of analog input data in BASE +
1 to form a complete 12-bit number. The data format is 0 = −FS; 4095 = +FS.
The channel number is binary. If the current channel is 5, bits CH2 and CH0 are high, CH3 and CH1 are
low.
WRITE
Writing any data to the register causes an immediate A/D conversion.
Table 6-1. Register Map
READ FUNCTION
A/D Data (Least significant)
A/D Data (Most significant)
Channel MUX
Digital 4-Bit Input
None
None
None
None
Status EOC, UNI/BIP etc.
DMA, Interrupt & Trigger
Control
none
PGA gain
Counter 0 Data
CTR 1 Data - A/D Pacer Clock
CTR 2 Data - A/D Pacer Clock
None. No read back on 8254
Port A Input of 8255
Port B Input
Port C Input
None. No read back on 8255
None
None
None
Status of extended features
5 4
A/D 1 A/D 0
LSB
20
WRITE FUNCTION
Start A/D Conversion
None
Channel MUX / FIFO reset
Digital 4 Bit Output
D/A 0 Least Significant bits
D/A 0 Most Significant bits
D/A 1 Least Significant bits
D/A 1 Most Significant bits
Clear Interrupt
Set DMA, INT etc
Burst Length/pacer clk cntrl
PGA Control/DT reset
Counter 0 Data
CTR 1 Data - A/D Pacer
CTR 2 Data - A/D Pacer
Pacer Clock Control (8254)
Port A Output, n/a on -P5 ver.
Port B Output, n/a on -P5 ver.
Port C Output, n/a on -P5 ver.
Configure 8255, n/a on -P5 ver.
Conversion Enable/Disable
Burst Mode Enable/Disable
DAS 1600 Enable/Disable
None
3 2
CH3 CH2
1 0
CH1 CH0