Ram - Edge-Core AS7326-56X Programming Manual

CPLD
U12
BDXDE
U9
LAN_FLASH_CS_N
BCM5720
U6

3.6. RAM

The BDXDE can support memory DDR3 and DDR4 that need via strap pin DDR3_4_STRAP to
configure which one be supported. The project support two DDR4 SODIMM with ECC that has to pull
DDR3_4_STRAP to high.
EDGECORE NETWORKS CORPORATION 2018
SPI_CS_SELECT
U2
mux
U32
SPI_CS1#
mux
SPI
LAN_FLASH_CK
LAN_FLASH_DO
U18
Level
shift
LAN_FLASH_DI
NVM_SI
SI
NVM_SO SO
NVM_SK SCK
CS#
NVM_CS_N
Figure 17 RAM Connection
BDX_SPI_MUX_SEL
SEL
BIOS_SPI_KGI_N B1
U44
A
BIOS_SPI_CS1 B0
MUX
BIOS_SPI_CI_N
1B2
BMC_SPI_CS0 1B1
2A/3A/4A
1A
U43
MUX
SPI_CLK_MOSI_MISO
B2
B1
OE#
SEL
BDX_SPI_MUX_SEL
BMC_CLK_DI_DO
B1
U42 BMC_SPI_CS_N
A
MUX
B0
SEL
BMC_SPI_OUT_SEL
SCK
U16
SI
CS#
32Mb
SO
U39
M45PE20
2Mb
OE#
BIOS_SPI2_CS_switch
Q1
CS1
BIOS_SPI2_CS
BIOS_SPI_CLK_DI_DO
Clk/di/do
Clk/di/do
CS0
BIOS_SPI1_CS
SPI_MUX_OE_N
119
133
CONN14
BMC
141
OE# S
U43 Function
L L
A=B1
A=B2(Default)
L H
Disconnect
H X
128Mb
U31
128Mb
U1
Q16
CS
CONN2
SF100_IO3
Jumper
CI_KGI_SELECT
CONN3
Dediprog
BIOS_SPI_CLK_DI_DO
S MUX Function
L B0=A
H B1=A(Default)
37