Sdram Cycle; Memory Hole; Read Around Write; Concurrent Pci/Host - SOLTEK SL-65D User Manual

SDRAM Cycle

Length Time

Memory Hole

Read Around Write

Concurrent
PCI/HOST
System BIOS
Cacheable
You can select CAS latency time in
HCLKs of 2/2 or 3/3. The system board
designer should have set the values in this
field, depending on the DRAM installed.
Do not change the values in this field
unless you change specifications of the
installed DRAM or the installed CPU.
Choose Enabled or Disabled (default).
In order to improve performance,
certain space in memory can be
reserved for ISA cards. This
memory must be mapped into the
memory's space below 16MB.
DRAM optimization feature: If a memory
read is addressed to a location whose latest
write is being held in a buffer before being
written to memory, the read is satisfied
through the buffer contents, and the read is
not sent to the DRAM
The Choice: Enabled, Disabled.
When disabled, CPU bus will be occupied
during the entire PCI operation period.
The Choice: Enabled, Disabled
Choose Enabled or Disabled
(default). When Enabled, the access
to the system BIOS ROM addressed
at F0000H-FFFFFH is cached.
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