Layout Requirements - Advantech SOM-5780 Design Manual

Table 5-16 LVDS Signals Trace Length Mismatch Mapping
Siganl group Data Pair
LVDS_A[0]+
LVDS_A[0]-
CHANNEL A
LVDS_A[1]+
LVDS_A[1]-
LVDS_A[2]+
LVDS_A[2]-
LVDS_A[3]+
LVDS_A[3]-
LVDS_B[0]+
LVDS_B[0]-
CHANNEL B
LVDS_B[1]+
LVDS_B[1]-
LVDS_B[2]+
LVDS_B[2]-
LVDS_B[3]+
LVDS_B[3]-

5.5.3 Layout Requirements

Routing for LVDS transmitter timing domain signals for different traces terminated
across 100Ω ± 15% and should be routed as follows.
It is necessary to maintain the differential impedance, Zdiff = 100Ω ± 15%, where
!
all traces are closely routed in the same area on the same layer.
Isolate all other signals from the LVDS signals to prevent coupling from other
!
sources onto the LVDS lines.
The LVDS transmitter timing domain signals have maximum trace length of 10
!
inches. Be sure that the max trace length routed on the carrier board is 7.5 inches.
Clocks must be matched to the associated data signals to within 10 mils.
!
Channel-to-Channel clock length must be matched to within 10 mils.
!
Minimum spacing between neighboring trace pair is 20 mils.
!
Traces must be ground referenced.
!
When choosing cables, it is important to remember that the differential
!
impedance of cable should be 100Ω and the length must be less than 16 inches.
SOM-Express
60
Advantech SOM-Express Design Guide
Clocks
Signal Associated
matching with the
channel
±10 mils
±10 mils
LVDS_A_CK+
LVDS_A_CK-
±10 mils
±10 mils
±10 mils
±10 mils
LVDS_B_CK+
LVDS_B_CK-
±10 mils
±10 mils
Carrier board
Min=20mils
Max=7.5 inches
Figure 5-23 LVDS Signal Routing Topology
Chapter 5 Carrier Board Design Guidelines
Data To
Clock Associated
Matching Clock
Matching
±10 mils ±10 mils
±10 mils ±10 mils
LVDS
connector
Receiver