Chapter 5 Carrier Board Design Guidelines; Pci-Bus; Signal Description - Advantech SOM-5780 Design Manual

Chapter 5 Carrier Board Design Guidelines

5.1 PCI-Bus

SOM-Express provides a PCI Bus interface that is compliant with the PCI Local Bus
Specification, Revision 2.3. The implementation is optimized for high-performance
data streaming when SOM-Express is acting as either the target or the initiator on the
PCI bus. For more information on the PCI Bus interface, please refer to the PCI Local
Bus Specification, Revision 2.3.

5.1.1 Signal Description

Table 5-1 shows SOM-Express PCI bus signal, including pin number, signals, I/0,
and descriptions.
Table 5.1 PCI Signal Description
Pin Signal
D50 PCI_CLK
D48 PCI_CLKRUN#
C22,C19,
PCI_REQ[0..3]
C17,D20
C20,C18,
PCI_GNT[0..3]
C16,D19
- PCI_AD[0..31]
D26,C33,
PCI_C/BE[0..3]
C38,C44
D32 PCI_PAR
D33 PCI_SERR#
C34 PCI_PERR#
C15 PME#
PCI_LOCK#
C35
C36 PCI_DEVSEL#
PCI_TRDY#
D35
PCI_IRDY#
C37
PCI_STOP#
D34
PCI_FRAME#
D36
PCI_RESET#
C23
C49,C50,
PCI_IRQ[A...D]
D46,D47
D49 PCI_M66EN
40
Advantech SOM-Express Design Guide
I/O Description
O PCI 33 MHz clock output
Bidirectional pin used to support PCI clock run protocol for
I/O
mobile systems
Bus Request signals for up to 4 external bus mastering PCI
I
devices. When asserted, a PCI device is requesting PCI bus
ownership from the arbiter.
Grant signals to PCI Masters. When asserted by the arbiter, the
O
PCI master has been granted ownership of the PCI bus.
PCI Address and Data Bus Lines. These lines carry the address
I/O
and data information for PCI transactions.
PCI Bus Command and Byte Enables. Bus command and byte
I/O enables are multiplexed in these lines for address and data
phases, respectively.
I/O Parity bit for the PCI bus.
I/O System Error. Asserted for hardware error conditions such as
OD parity errors detected in DRAM.
Parity Error. For PCI operation per exception granted by PCI 2.1
I/O
Specification.
I Power management event.
Lock Resource Signal. This pin indicates that either the PCI
I/O
master or the bridge intends to run exclusive transfers.
Device Select, active low. When the target device has decoded
I/O
the address as its own cycle, it will assert DEVSEL#.
Target Ready. This pin indicates that the target is ready to
I/O
complete the current data phase of a transaction.
Initiator Ready. This signal indicates that the initiator is ready to
I/O
complete the current data phase of a transaction.
Stop. This signal indicates that the target is requesting that the
I/O
master stop the current transaction.
Cycle Frame of PCI Buses. This indicates the beginning and
I/O
duration of a PCI access.
PCI Bus Reset. This is an output signal to reset the entire PCI
I
Bus. This signal is asserted during system reset.
I PCI interrupt request lines.
Module input signal indicates whether an off-module PCI device
is capable of 66 MHz operation. Pulled to GND by Carrier Board
device or by Slot Card if the devices are NOT capable of 66
MHz operation.
I If the module is not capable of supporting 66 MHz PCI
operation, this input may be a no-connect on the module.
If the module is capable of supporting 66 MHz PCI operation,
and if this input is held low by the Carrier Board, the module PCI
interface shall operate at 33 MHz.
Chapter 5 Carrier Board Design Guidelines