Silicon Laboratories EFM8BB2-SLSTK2021A User Manual page 12

Peripheral Peripheral pin
Comparator 0 CMP0P Positive Input Any supported pin (see Reference Manual for more information)
CMP0N Negative In-
put
Comparator 1 CMP1P Positive Input Any supported pin (see Reference Manual for more information)
CMP1N Negative In-
put
Note: This table only sums up some of the alternate functions available on the expansion header. Consult the EFM8BB22F16G data
sheet for a complete list of alternate functions.
6.3 Debug Connector
This connector is used for Debug In and Debug Out (see chapter on Debugging).
Pin num- Function
ber
1 VTARGET
2 TMS/SWDIO/C2D
4 TCK/SWCLK/C2CK
6 TDO/SWO
8 TDI
9 ATTACH
10 #RESET
12 TRACECLK
14, 16, TRACED0-3
18, 20
11, 13 NC
3, 5, 15, GND
17, 19
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MCU Pin
Any supported pin (see Reference Manual for more information)
Any supported pin (see Reference Manual for more information)
Figure 6.3. Debug Connector
Table 6.2. Debug Connector Pinout
Note
Target voltage on the debugged application.
Note: This connection is required and is needed for the debug circuitry to match voltage levels
with the target device.
JTAG TMS, Serial Wire data I/O, or EFM8 C2 data I/O
JTAG TCK, Serial Wire clock, or EFM8 C2 clock
JTAG TDO or Serial Wire Output
JTAG data in
This signal must be pulled to ground by the external debugger or application for cable insertion
detection.
Target MCU reset.
Trace clock
Trace data (4 lines)
Not Connected
UG237: EFM8BB2-SLSTK2021A User's Guide
Connectors
EXP Header pin
number
Multiple
Multiple
Multiple
Multiple
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