Silicon Laboratories EFM32G Reference Manual

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...the world's most energy friendly microcontrollers

EFM32G Reference Manual

Gecko Series

• 32-bit ARM Cortex-M3 processor running at up to 32 MHz

• Up to 128 kB Flash and 16 kB RAM memory

• Energy efficient and autonomous peripherals

• Ultra low power Energy Modes with sub-µA operation

• Fast wake-up time of only 2 µs

The EFM32G microcontroller series revolutionizes the 8- to 32-bit market with a

combination of unmatched performance and ultra low power consumption in both

active- and sleep modes. EFM32G devices consume as little as 180 µA/MHz in run

mode, and as little as 900 nA with a Real Time Counter running, Brown-out and full

RAM and register retention.

EFM32G's low energy consumption outperforms any other available 8-, 16-, and 32-

bit solution. The EFM32G includes autonomous and energy efficient peripherals,

high overall chip- and analog integration, and the performance of the industry

standard 32-bit ARM Cortex-M3 processor.

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Summary of Contents for Silicon Laboratories EFM32G

Page 1 EFM32G devices consume as little as 180 µA/MHz in run mode, and as little as 900 nA with a Real Time Counter running, Brown-out and full RAM and register retention.
Page 2: Energy Friendly Microcontrollers
1 Energy Friendly Microcontrollers 1.1 Typical Applications The EFM32G Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications. These devices are developed to minimize the energy consumption by lowering both the power and the active time, over all phases of MCU operation. This unique combination of ultra low energy consumption and the performance of the 32-bit ARM Cortex-M3 processor, help designers get more out of the available energy in a variety of applications.
Page 3: About This Document
This document contains reference material for the EFM32G series of microcontrollers. All modules and peripherals in the EFM32G series devices are described in general terms. Not all modules are present in all devices, and the feature set for each device might vary. Such differences, including pin-out, are covered in the device-specific datasheets.
Page 4: Related Documentation
USn_TX (USARTn TX pin) The pin locations referenced in this document are given in the device-specific datasheet. 2.2 Related Documentation Further documentation on the EFM32G family and the ARM Cortex-M3 can be found at the Silicon Laboratories and ARM web pages: www.silabs.com www.arm.com...
Page 5: System Overview
32-bit ARM Cortex-M3, innovative low energy techniques, short wake-up time from energy saving modes, and a wide selection of peripherals, the EFM32G microcontroller is well suited for any battery operated application, as well as other systems requiring high performance and low-energy consumption, see Figure 3.1 (p.
Page 6: Block Diagram
• LQFP100 • LFBGA112 3.3 Block Diagram Figure 3.1 (p. 7) shows the block diagram of EFM32G. The color indicates peripheral availability in the different energy modes, described in Section 3.4 (p. 7) . www.silabs.com 2014-07-02 - Gecko Family - d0001_Rev1.30...
Page 7: Energy Modes
In the energy mode indicator, the numbers indicates Energy Mode, i.e EM0-EM4. 3.4 Energy Modes There are five different Energy Modes (EM0-EM4) in the EFM32G, see Table 3.1 (p. 8) . The EFM32G is designed to achieve a high degree of autonomous operation in low energy modes. The...
Page 8: Product Overview
(Shutoff Mode) state. 3.5 Product Overview Table 3.2 (p. 8) shows a device overview of the EFM32G Microcontroller Series, including peripheral functionality. For more information, the reader is referred to the device specific datasheets. Table 3.2. EFM32G Microcontroller Series 200F16...
Page 9: Device Revision
...the world's most energy friendly microcontrollers 230F32 2 (2) QFN64 (16) 230F64 2 (2) QFN64 (16) 230F128 2 (2) QFN64 (16) 280F32 2 (2) LQFP100 (16) 280F64 2 (2) LQFP100 (16) 280F128 2 (2) LQFP100 (16) 290F32 2 (2) LFBGA112 (16) 290F64 2 (2)
Page 10: Minor Revision Number Interpretation
...the world's most energy friendly microcontrollers Figure 3.3. Revision Number Extraction PID2 (0 xE0 0 FFFE8 ) PID3 (0 xE0 0 FFFEC) 31:8 31:8 Minor Rev[7:4] Minor Rev[3:0] PID0 (0 xE0 0 FFFE0 ) PID1 (0 xE0 0 FFFE4 ) 31:7 31:4 Fam [1:0]...
Page 11: System Processor
...the world's most energy friendly microcontrollers 4 System Processor Quick Facts What? 0 1 2 3 The industry leading Cortex-M3 processor from ARM is the CPU in the EFM32G microcontrollers. Why? CM3 Core The ARM Cortex-M3 is designed for exceptional short response time, high...
Page 12: Functional Description
Software generated interrupt The EFM32G devices have up to 30 interrupt request lines (IRQ) which are connected to the Cortex-M3. Each of these lines (shown in Table 4.1 (p. 12) ) are connected to one or more interrupt flags in one or more modules.
Page 13: Lcd
...the world's most energy friendly microcontrollers IRQ # Source TIMER1 TIMER2 USART1_RX USART1_TX USART2_RX USART2_TX UART0_RX UART0_TX LEUART0 LEUART1 LETIMER0 PCNT0 PCNT1 PCNT2 VCMP www.silabs.com 2014-07-02 - Gecko Family - d0001_Rev1.30...
Page 14: Memory And Bus System
5.1 Introduction The EFM32G contains an AMBA AHB Bus system allowing bus masters to access the memory mapped address space. A multilayer AHB bus matrix, using a Round-robin arbitration scheme, connects the master bus interfaces to the AHB slaves (Figure 5.1 (p. 15) ). The bus matrix allows several AHB slaves to be accessed simultaneously.
Page 15: Functional Description
...the world's most energy friendly microcontrollers Figure 5.1. EFM32G Bus System Flash Cortex AHB Multilayer Bus Matrix ICode DCode System Peripheral 0 AHB/ APB Bridge Peripheral n 5.2 Functional Description The memory segments are mapped together with the internal segments of the Cortex-M3 into the system memory map shown by Figure 5.2 (p.
Page 16: Memory Sram Area Set/Clear Bit
...the world's most energy friendly microcontrollers Figure 5.2. System Address Space The embedded SRAM is located at address 0x20000000 in the memory map of the EFM32G. When running code located in SRAM starting at this address, the Cortex-M3 uses the System bus to fetch instructions.
Page 17: Memory System Core Peripherals
...the world's most energy friendly microcontrollers bit_address = 0x22000000 + (address – 0x20000000) × 32 + bit × 4, (5.1) where address is the address of the 32-bit word containing the bit to modify, and bit is the index of the bit in the 32-bit word.
Page 18: Memory System Low Energy Peripherals
...the world's most energy friendly microcontrollers Table 5.2. Memory System Low Energy Peripherals Low energy peripherals Address range Peripheral 0x4008A400 – 0x400BFFFF Reserved 0x4008A000 – 0x4008A3FF 0x40088400 – 0x40089FFF Reserved 0x40088000 – 0x400883FF WDOG 0x40086C00 – 0x40087FFF Reserved 0x40086800 – 0x40086BFF PCNT2 0x40086400 –...
Page 19: Memory System Peripherals
...the world's most energy friendly microcontrollers Table 5.3. Memory System Peripherals Peripherals Address range Peripheral 0x40010C00 – 0x4007FFFF Reserved 0x40010800 – 0x40010BFF TIMER2 0x40010400 – 0x400107FF TIMER1 0x40010000 – 0x400103FF TIMER0 0x4000E400 – 0x4000FFFF Reserved 0x4000E000 – 0x4000E3FF UART0 0x4000CC00 – 0x4000DFFF Reserved 0x4000C800 –...
Page 20: Access To Low Energy Peripherals (Asynchronous Registers)
...the world's most energy friendly microcontrollers 5.2.3.2 Access Performance The Bus Matrix is a multi-layer energy optimized AMBA AHB compliant bus with an internal bandwidth equal to 4 times a single AHB-bus. The Bus Matrix accepts new transfers initiated by each master in every clock cycle without inserting any wait-states.
Page 21: Write Operation To Low Energy Peripherals
...the world's most energy friendly microcontrollers 5.3.1.1 Writing Every Low Energy Peripheral has one or more registers with data that needs to be synchronized into the Low Energy clock domain to maintain data consistency and predictable operation. Due to synchronization, the write operation requires 3 positive edges of the clock of the Low Energy Peripheral being accessed.
Page 22: Flash
...the world's most energy friendly microcontrollers Figure 5.4. Read operation from Low Energy Peripherals Core Clock Dom ain Low Frequency Clock Dom ain Freeze Core Clock Low Frequency Clock Low Frequency Clock Register 0 Synchronizer 0 Register 0 Sync Register 1 Synchronizer 1 Register 1 Sync Register n...
Page 23: Device Information (Di) Page
...the world's most energy friendly microcontrollers • Data retention of the entire memory in EM0 to EM3 5.6 Device Information (DI) Page The DI page contains calibration values, a unique identification number and other useful data. See the table below for a complete overview. Table 5.4.
Page 24 ...the world's most energy friendly microcontrollers DI Address Register Description 0x0FE081DF HFRCO_CALIB_BAND_14 [7:0]: Tuning for the 14 MHZ HFRCO band. 0x0FE081E0 HFRCO_CALIB_BAND_21 [7:0]: Tuning for the 21 MHZ HFRCO band. 0x0FE081E1 HFRCO_CALIB_BAND_28 [7:0]: Tuning for the 28 MHZ HFRCO band. 0x0FE081E7 MEM_INFO_PAGE_SIZE [7:0] Flash page size in bytes coded as 2 ^...
Page 25: Dbg - Debug Interface
6.1 Introduction The EFM32G devices include hardware debug support through a 2-pin serial-wire debug (SWD) interface. In addition, there is also a Serial Wire Viewer pin which can be used to output profiling information, data trace and software-generated messages.
Page 26: Debug Lock And Device Erase
...the world's most energy friendly microcontrollers • Serial Wire Clock input (SWCLK): This pin is enabled after reset and has a built-in pull down. • Serial Wire Data Input/Output (SWDIO): This pin is enabled after reset and has a built-in pull-up. •...
Page 27: Device Unlock
...the world's most energy friendly microcontrollers Figure 6.2. Device Unlock Reset Program ex ecution Locked No access Program 150 us ex ecution Unlocked No access Cortex 47 us If the device is locked, it can be unlocked by writing a valid key to the AAP_CMDKEY register and then setting the DEVICEERASE bit of the AAP_CMD register via the debug interface.
Page 28: Register Map
...the world's most energy friendly microcontrollers 6.5 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 AAP_CMD Command Register 0x004 AAP_CMDKEY Command Key Register 0x008 AAP_STATUS Status Register 0x0FC AAP_IDR AAP Identification Register 6.6 Register Description 6.6.1 AAP_CMD - Command Register Offset...
Page 29 ...the world's most energy friendly microcontrollers Name Reset Access Description The key value must be written to this register to write enable the AAP_CMD register. After AAP_CMD is written, this register should be cleared to excecute the command. Value Mode Description 0xCFACC118 WRITEEN...
Page 30: Msc - Memory System Controller
7.1 Introduction The Memory System Controller (MSC) is the program memory unit of the EFM32G microcontroller. The flash memory is readable and writable from both the Cortex-M3 and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code is normally written to the main block.
Page 31: Functional Description
...the world's most energy friendly microcontrollers • Conditional branch target prefetch suppression • Cortex-M3 disfolding of if-then (IT) blocks • DMA read support in EM0 and EM1 • Command and status interface • Flash write and erase • Accessible from Cortex-M3 in EM0 •...
Page 32: Lock Bits
...the world's most energy friendly microcontrollers 7.3.1 User Data (UD) Page Description This is the user data page in the information block. The page can be erased and written by software. The page is erased by the ERASEPAGE command of the MSC_WRITECMD register. Note that the page is not erased by a device erase operation.
Page 33 ...the world's most energy friendly microcontrollers 7.3.4.1 One Wait-state Access After reset, the HFCORECLK is normally 14 MHz from the HFRCO and the MODE field of the MSC_READCTRL register is set to WS1 (one wait-state). The reset value must be WS1 as an uncalibrated HFRCO may produce a frequency higher than 16 MHz.
Page 34 ...the world's most energy friendly microcontrollers addressed is locked. Any attempts to command erase of or write to the page are ignored if INVADDR or the LOCKED bits of the MSC_STATUS register are set. When a word is written to the MSC_WDATA register, the WDATAREADY bit of the MSC_STATUS register is cleared.
Page 35: Register Map
...the world's most energy friendly microcontrollers 7.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 MSC_CTRL Memory System Control Register 0x004 MSC_READCTRL Read Control Register 0x008 MSC_WRITECTRL Write Control Register 0x00C MSC_WRITECMD Write Command Register...
Page 36 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) MODE Read Mode If software wants to set a core clock frequency above 16 MHz, this register must be set to WS1 or WS1SCBTP before the core clock is switched to the higher frequency.
Page 37 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) WRITETRIG Word Write Sequence Trigger Functions like MSC_CMD_WRITEONCE, but will set MSC_STATUS_WORDTIMEOUT if no new data is written to MSC_WDATA within the 30 µs timeout.
Page 38 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:0 WDATA 0x00000000 Write Data The data to be written to the address in MSC_ADDR. This register must be written when the WDATAREADY bit of MSC_STATUS is set, otherwise the data is ignored. This register is not retained when entering EM2 or lower energy modes. 7.5.7 MSC_STATUS - Status Register Offset Bit Position...
Page 39 ...the world's most energy friendly microcontrollers Name Reset Access Description WRITE Write Done Interrupt Read Flag Set when a write is done. ERASE Erase Done Interrupt Read Flag Set when erase is done. 7.5.9 MSC_IFS - Interrupt Flag Set Register Offset Bit Position 0x030...
Page 40 ...the world's most energy friendly microcontrollers 7.5.11 MSC_IEN - Interrupt Enable Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) WRITE Write Done Interrupt Enable Enable the write done interrupt.
Page 41: Dma - Dma Controller
...the world's most energy friendly microcontrollers 8 DMA - DMA Controller Quick Facts What? 0 1 2 3 The DMA controller can move data without CPU intervention, effectively reducing the energy consumption for a data transfer. Why? The DMA can perform data transfers more Flash energy efficiently than the CPU and allows autonomous operation in low energy modes.
Page 42: Block Diagram
...the world's most energy friendly microcontrollers • Ping-pong (switching between the primary or alternate DMA descriptors, for continuous data flow to/from peripherals) • Scatter-gather (using the primary descriptor to configure the alternate descriptor) • Each channel has a programmable transfer length •...
Page 43: Functional Description
...the world's most energy friendly microcontrollers • A channel select block routing the right peripheral request to each DMA channel 8.4 Functional Description The DMA Controller is highly flexible. It is capable of transferring data between peripherals and memory without involvement from the processor core. This can be used to increase system performance by off-loading the processor from copying large amounts of data or avoiding frequent interrupts to service peripherals needing more data or having available data.
Page 44: Ahb Bus Transfer Arbitration Interval
...the world's most energy friendly microcontrollers and this determines the arbitration rate. For example, if R = 4 then the arbitration rate is 2 , that is, the controller arbitrates every 16 DMA transfers. Table 8.1 (p. 44) lists the arbitration rates. Table 8.1.
Page 45 ...the world's most energy friendly microcontrollers Channel Priority level Descending order of number setting channel priority High High High High High Default Default Default Default Default Default Default Default Lowest-priority DMA channel After a DMA transfer completes, the controller polls all the DMA channels that are available. Figure 8.2 (p. 45) shows the process it uses to determine which DMA transfer to perform next.
Page 46: Dma Cycle Types
...the world's most energy friendly microcontrollers Table 8.3. DMA cycle types cycle_ctrl Description b000 Channel control data structure is invalid b001 Basic DMA transfer b010 Auto-request b011 Ping-pong b100 Memory scatter-gather using the primary data structure b101 Memory scatter-gather using the alternate data structure b110 Peripheral scatter-gather using the primary data structure b111...
Page 47 ...the world's most energy friendly microcontrollers 2. The controller arbitrates. When channel C has the highest priority then the DMA cycle continues at step 1 (p. 46) . 3. The controller sets dma_done[C] HIGH for one HFCORECLK cycle. This indicates to the host processor that the DMA cycle is complete.
Page 48 ...the world's most energy friendly microcontrollers 5. The controller performs the remaining two DMA transfers. 6. The controller sets dma_done[C] HIGH for one HFCORECLK cycle and enters the arbitration process. After task A completes, the host processor can configure the primary data structure for task C. This enables the controller to immediately switch to task C after task B completes, provided that a higher priority channel does not require servicing.
Page 49: Channel_Cfg For A Primary Data Structure, In Memory Scatter-Gather Mode
...the world's most energy friendly microcontrollers and on completion of task D the controller set the cycle_ctrl bits to b000, then the ping-pong DMA transaction completes. Note You can also terminate the ping-pong DMA cycle in Figure 8.3 (p. 47) , if you configure task E to be a basic DMA cycle by setting the cycle_ctrl field to 3’b001.
Page 50: Memory Scatter-Gather Example
...the world's most energy friendly microcontrollers Figure 8.4. Memory scatter-gather example Initialization: 1. Configure prim ary to enable the copy A, B, C, and D operations: cycle_ctrl = b100, 2 = 4, N = 16. 2. Write the prim ary source data to m em ory, using the structure shown in the following table. src_data_end_ptr dst_data_end_ptr channel_cfg...
Page 51: Channel_Cfg For A Primary Data Structure, In Peripheral Scatter-Gather Mode
...the world's most energy friendly microcontrollers 8. The controller generates an auto-request for the channel and then arbitrates. Task C 9. The controller performs task C. After it completes the task, it generates an auto-request for the channel and then arbitrates. Primary, copy D 10.
Page 52: Peripheral Scatter-Gather Example
...the world's most energy friendly microcontrollers Field Value Description [20:18] src_prot_ctrl Configures the state of HPROT when the controller reads the source data [13:4] n_minus_1 Configures the controller to perform N DMA transfers, where N is a multiple of four next_useburst When set to 1, the controller sets the chnl_useburst_set [C] bit to 1 after the alternate transfer completes...
Page 53 ...the world's most energy friendly microcontrollers Primary, copy A 1. After receiving a request, the controller performs four DMA transfers. These transfers write the alternate data structure for task A. Task A 2. The controller performs task A. 3. After the controller completes the task it enters the arbitration process. After the peripheral issues a new request and it has the highest priority then the process continues with: Primary, copy B 4.
Page 54: Address Bit Settings For The Channel Control Data Structure
...the world's most energy friendly microcontrollers • provide a contiguous area of system memory that the controller and host processor can access • have a base address that is an integer multiple of the total size of the channel control data structure. Figure 8.6 (p.
Page 55: Src_Data_End_Ptr Bit Assignments
...the world's most energy friendly microcontrollers Figure 8.7 (p. 55) shows a detailed memory map of the descriptor structure. Figure 8.7. Detailed memory map for the 8 channels, including the alternate data structure Unused 0x 0FC Control Alternate for 0x 0F8 channel 7 Destination End Pointer 0x 0F4...
Page 56: Channel_Cfg Bit Assignments
...the world's most energy friendly microcontrollers 8.4.3.2 Destination data end pointer The dst_data_end_ptr memory location contains a pointer to the end address of the destination data. Table 8.8 (p. 56) lists the bit assignments for this memory location. Table 8.8. dst_data_end_ptr bit assignments Name Description [31:0]...
Page 57 ...the world's most energy friendly microcontrollers Name Description b11 = no increment. Address remains set to the value that the dst_data_end_ptr memory location contains. [29:28] dst_size Destination data size. Note You must set dst_size to contain the same value that src_size contains. [27:26] src_inc Set the bits to control the source address increment.
Page 58 ...the world's most energy friendly microcontrollers Name Description b1000 Arbitrates after 256 DMA transfers. b1001 Arbitrates after 512 DMA transfers. b1010 - b1111 Arbitrates after 1024 DMA transfers. This means that no arbitration occurs during the DMA transfer because the maximum transfer size is 1024. [13:4] n_minus_1 Prior to the DMA cycle commencing, these bits represent the total number of DMA transfers...
Page 59: Dma Cycle Of Six Words Using A Word Increment
...the world's most energy friendly microcontrollers Name Description When the controller operates in peripheral scatter-gather mode, you must only use this value in the primary data structure. b111 Peripheral scatter/gather. See Section 8.4.2.3.6 (p. 51) . When the controller operates in peripheral scatter-gather mode, you must only use this value in the alternate data structure.
Page 60: Examples
...the world's most energy friendly microcontrollers Table 8.11 (p. 60) lists the destination addresses for a DMA transfer of 12 bytes using a halfword increment. Table 8.11. DMA cycle of 12 bytes using a halfword increment Initial values of channel_cfg, prior to the DMA cycle src_size = b00, dst_inc = b01, n_minus_1 = b1011, cycle_ctrl = 1, R_power = b11 End Pointer Count...
Page 61 ...the world's most energy friendly microcontrollers Example 8.1. DMA Transfer 1. Configure the channel select for using USART1 with DMA channel 0 a. Write SOURCESEL=0b001101 and SIGSEL=XX to DMA_CHCTRL0 2. Configure the primary channel descriptor for DMA channel 0 a. Write XX (read address of USART1) to src_data_end_ptr b.
Page 62: Register Map
...the world's most energy friendly microcontrollers 8.6 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 DMA_STATUS DMA Status Registers 0x004 DMA_CONFIG DMA Configuration Register 0x008 DMA_CTRLBASE Channel Control Data Base Pointer Register 0x00C DMA_ALTCTRLBASE Channel Alternate Control Data Base Pointer Register...
Page 63: Register Description
...the world's most energy friendly microcontrollers 8.7 Register Description 8.7.1 DMA_STATUS - DMA Status Registers Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:21 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 20:16 CHNUM 0x07...
Page 64 ...the world's most energy friendly microcontrollers Name Reset Access Description Control whether accesses done by the DMA controller are privileged or not. When CHPROT = 1 then HPROT is HIGH and the access is privileged. When CHPROT = 0 then HPROT is LOW and the access is non-privileged. Reserved To ensure compatibility with future devices, always write bits to 0.
Page 65 ...the world's most energy friendly microcontrollers 8.7.5 DMA_CHWAITSTATUS - Channel Wait on Request Status Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CH7WAITSTATUS Channel 7 Wait on Request Status Status for wait on request for channel 7.
Page 66 ...the world's most energy friendly microcontrollers Name Reset Access Description CH5SWREQ Channel 5 Software Request Write 1 to this bit to generate a DMA request for this channel. CH4SWREQ Channel 4 Software Request Write 1 to this bit to generate a DMA request for this channel. CH3SWREQ Channel 3 Software Request Write 1 to this bit to generate a DMA request for this channel.
Page 67 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description SINGLEANDBURST Channel responds to both single and burst requests BURSTONLY Channel responds to burst requests only 8.7.8 DMA_CHUSEBURSTC - Channel Useburst Clear Register Offset Bit Position 0x01C Reset Access Name...
Page 68 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CH7REQMASKS Channel 7 Request Mask Set Write to 1 to disable peripheral requests for this channel. CH6REQMASKS Channel 6 Request Mask Set Write to 1 to disable peripheral requests for this channel.
Page 69 ...the world's most energy friendly microcontrollers Name Reset Access Description CH0REQMASKC Channel 0 Request Mask Clear Write to 1 to enable peripheral requests for this channel. 8.7.11 DMA_CHENS - Channel Enable Set Register Offset Bit Position 0x028 Reset Access Name Name Reset Access...
Page 70 ...the world's most energy friendly microcontrollers Name Reset Access Description CH7ENC Channel 7 Enable Clear Write to 1 to disable this channel. See also description for channel 0. CH6ENC Channel 6 Enable Clear Write to 1 to disable this channel. See also description for channel 0. CH5ENC Channel 5 Enable Clear Write to 1 to disable this channel.
Page 71 ...the world's most energy friendly microcontrollers Name Reset Access Description CH0ALTS Channel 0 Alternate Structure Set Write to 1 to select the alternate structure for this channel. 8.7.14 DMA_CHALTC - Channel Alternate Clear Register Offset Bit Position 0x034 Reset Access Name Name Reset...
Page 72 ...the world's most energy friendly microcontrollers Name Reset Access Description CH7PRIS Channel 7 High Priority Set Write to 1 to obtain high priority for this channel. Reading returns the channel priority status. CH6PRIS Channel 6 High Priority Set Write to 1 to obtain high priority for this channel. Reading returns the channel priority status. CH5PRIS Channel 5 High Priority Set Write to 1 to obtain high priority for this channel.
Page 73 ...the world's most energy friendly microcontrollers Name Reset Access Description Write to 1 to clear high priority for this channel. 8.7.17 DMA_ERRORC - Bus Error Clear Register Offset Bit Position 0x04C Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 74 ...the world's most energy friendly microcontrollers Name Reset Access Description When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel. The controller services the request by performing the DMA cycle using 2 DMA transfers.
Page 75 ...the world's most energy friendly microcontrollers 8.7.20 DMA_IF - Interrupt Flag Register Offset Bit Position 0x1000 Reset Access Name Name Reset Access Description DMA Error Interrupt Flag This flag is set when an error has occurred on the AHB bus. 30:8 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 76 ...the world's most energy friendly microcontrollers Name Reset Access Description CH6DONE DMA Channel 6 Complete Interrupt Flag Set Write to 1 to set the corresponding DMA channel complete interrupt flag. CH5DONE DMA Channel 5 Complete Interrupt Flag Set Write to 1 to set the corresponding DMA channel complete interrupt flag. CH4DONE DMA Channel 4 Complete Interrupt Flag Set Write to 1 to set the corresponding DMA channel complete interrupt flag.
Page 77 ...the world's most energy friendly microcontrollers 8.7.23 DMA_IEN - Interrupt Enable register Offset Bit Position 0x100C Reset Access Name Name Reset Access Description DMA Error Interrupt Flag Enable Set this bit to enable interrupt on AHB bus error. 30:8 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 78 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description 0b000000 NONE No source selected 0b001000 ADC0 Analog to Digital Converter 0 0b001010 DAC0 Digital to Analog Converter 0 0b001100 USART0 Universal Synchronous/Asynchronous Receiver/Transmitter 0 0b001101 USART1 Universal Synchronous/Asynchronous Receiver/Transmitter 1 0b001110 USART2...
Page 79 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description SOURCESEL 0b011000 (TIMER0) 0b0000 TIMER0UFOF TIMER0UFOF 0b0001 TIMER0CC0 TIMER0CC0 0b0010 TIMER0CC1 TIMER0CC1 0b0011 TIMER0CC2 TIMER0CC2 SOURCESEL 0b011001 (TIMER1) 0b0000 TIMER1UFOF TIMER1UFOF 0b0001 TIMER1CC0 TIMER1CC0 0b0010 TIMER1CC1 TIMER1CC1 0b0011 TIMER1CC2 TIMER1CC2...
Page 80: Rmu - Reset Management Unit
9.3 Functional Description The RMU monitors each of the reset sources of the EFM32G. If one or more reset sources go active, the RMU applies reset to the EFM32G. When the reset sources go inactive the EFM32G starts up. At startup the EFM32G loads the stack pointer and program entry point from memory, and starts execution.
Page 81: Rmu Reset Cause Register Interpretation
...the world's most energy friendly microcontrollers Figure 9.1. RMU Reset Input Sources and Connections. Reset Managem ent Unit POWERONn Cortex - M3 BROWNOUT_UNREGn Debug Interface PORESETn BROWNOUT_REGn DD_REGULATED RESETn Filter Core RCCLR RMU_RSTCAUSE WDOG SYSRESETn Peripherals LOCKUP Edge- to- pulse filter LOCKUPRDIS SYSREQRST...
Page 82 9.3.3 Brown-Out Detector Reset (BOD) The EFM32G has 2 brownout detectors, one for the unregulated 3.0 V power and one for the internal 1.8 V power. The BODs are constantly monitoring the voltages. Whenever the voltage is below the VBODthr value (see Electrical Characteristics for details), the corresponding active low BROWNOUTn line is held low.
Page 83 ...the world's most energy friendly microcontrollers 9.3.5 Watchdog Reset The Watchdog circuit is a timer which (when enabled) must be cleared by software regularly. If software does not clear it, a Watchdog reset is activated. This functionality provides recovery from a software stalemate.
Page 84: Register Map
...the world's most energy friendly microcontrollers 9.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 RMU_CTRL Control Register 0x004 RMU_RSTCAUSE Reset Cause Register 0x008 RMU_CMD Command Register 9.5 Register Description 9.5.1 RMU_CTRL - Control Register Offset Bit Position...
Page 85 ...the world's most energy friendly microcontrollers Name Reset Access Description EXTRST External Pin Reset Set if an external pin reset has been performed. Must be cleared by software. Please see Table 9.1 (p. 81) for details on how to interpret this bit. BODREGRST Brown Out Detector Regulated Domain Reset Set if a regulated domain brown out detector reset has been performed.
Page 86: Emu - Energy Management Unit
10.1 Introduction The Energy Management Unit (EMU) manages all the low energy modes (EM) in EFM32G microcontrollers. Each energy mode manages if the CPU and the various peripherals are available. The energy modes range from EM0 to EM4, where EM0, also called run mode, enables the CPU and all peripherals.
Page 87: Functional Description
10.3 Functional Description The Energy Management Unit (EMU) is responsible for managing the wide range of energy modes available in EFM32G. An overview of the EMU module is shown in Figure 10.1 (p. 87) . Figure 10.1. EMU Overview Peripheral bus...
Page 88 ...the world's most energy friendly microcontrollers Figure 10.2. EMU Energy Mode Transitions Active m ode Low energy m odes No direct transitions between EM1, EM2 or EM3 are available, as can also be seen from Figure 10.2 (p. 88) . Instead, a wakeup will transition back to EM0, in which software can enter any other low energy mode.
Page 89: Emu Energy Mode Overview
...the world's most energy friendly microcontrollers Table 10.1. EMU Energy Mode Overview Wakeup time to EM0 2 µs 2 µs 160 µs MCU clock tree High frequency peripheral clock trees Core voltage regulator High frequency oscillator C full functionality Low frequency peripheral clock trees Low frequency oscillator Real Time Counter LEUART...
Page 90: Emu Entering A Low Energy Mode
...the world's most energy friendly microcontrollers • The high frequency peripheral and MCU clock trees are inactive • The low frequency oscillator and clock trees are active • Low frequency peripheral functionality is available • Wakeup through peripheral interrupt or asynchronous pin interrupt •...
Page 91: Emu Wakeup Triggers From Low Energy Modes
...the world's most energy friendly microcontrollers in Table 10.3 (p. 91) . The wakeup triggers always return the EFM32 to EM0. Additionally, any reset source will return to EM0. Table 10.3. EMU Wakeup Triggers from Low Energy Modes Peripheral Wakeup Trigger Any enabled interrupt USART Receive / transmit...
Page 92: Register Map
...the world's most energy friendly microcontrollers 10.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 EMU_CTRL Control Register 0x004 EMU_MEMCTRL Memory Control Register 0x008 EMU_LOCK Configuration Lock Register 0x024 EMU_AUXCTRL Auxiliary Control Register 10.5 Register Description 10.5.1 EMU_CTRL - Control Register...
Page 93 ...the world's most energy friendly microcontrollers Name Reset Access Description POWERDOWN RAM block power-down Individual 32KB RAM block power-down. When a block is powered down, it cannot be powered up again. The block will be powered up after the reset. Block 0 (address range 0x20000000-0x20007FFF) may never be powered down. Value Mode Description...
Page 94 ...the world's most energy friendly microcontrollers Name Reset Access Description Write to 1 and then 0 to clear the POR, BOD and WDOG reset cause register bits. See also the Reset Management Unit (RMU). www.silabs.com 2014-07-02 - Gecko Family - d0001_Rev1.30...
Page 95: Cmu - Clock Management Unit
The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board the EFM32G. The CMU provides the capability to turn on and off the clock on an individual basis to all peripheral modules in addition to enable/disable and configure the available oscillators. The high degree of flexibility enables software to minimize energy consumption in any specific application by not wasting power on peripherals and oscillators that are inactive.
Page 96: Functional Description
...the world's most energy friendly microcontrollers • Clock Gating on an individual basis to core modules and all peripherals • Selectable clocks can be output on two pins for use externally. • Auxiliary 14 MHz RC oscillator (AUXHFRCO) for flash programming and debug trace. 11.3 Functional Description An overview of the CMU is shown in Figure 11.1 (p.
Page 97: Cmu Overview
...the world's most energy friendly microcontrollers Figure 11.1. CMU Overview AUXCLK Debug Trace AUXHFRCO Tim eout (Flash Program m ing) CMU_HFPERCLKEN0.TIMER0 Clock HFPERCLK TIMER0 Gate CMU_HFPERCLKEN0.TIMER1 HFPERCLK Clock TIMER1 Gate CMU_HFPERCLKDIV.HFPERCLKEN HFPERCLK prescaler CMU_HFPERCLKEN0.I2C0 CMU_HFPERCLKDIV.HFPERCLKDIV HFPERCLK Clock I2C0 Gate HFXO Tim eout HFCLK clock...
Page 98 ...the world's most energy friendly microcontrollers oscillator (HFRCO or HFXO) or one of the low-frequency oscillators (LFRCO or LFXO). By default the HFRCO is selected. In most applications, one of the high frequency oscillators will be the preferred choice. To change the selected HFCLK write to HFCLKSEL in CMU_CMD. The HFCLK is running in EM0 and EM1.
Page 99 ...the world's most energy friendly microcontrollers Each Low Energy Peripheral that is clocked by LFBCLK has its own prescaler setting and enable bit. The prescaler settings are configured using CMU_LFBPRESC0 and the clock enable bits can be found in CMU_LFBCLKEN0. 11.3.1.6 PCNTnCLK - Pulse Counter n Clock Each available pulse counter is driven by its own clock, PCNTnCLK where n is the pulse counter instance number.
Page 100: Cmu Switching From Hfrco To Hfxo Before Hfxo Is Ready
...the world's most energy friendly microcontrollers During the start-up period HFCLK will stop since the oscillator driving it is not ready. This effectively stalls the Core Modules and the High-Frequency Peripherals. It is possible to avoid this by first enabling the HFXO and then wait for the oscillator to become ready before switching the clock source.
Page 101 ...the world's most energy friendly microcontrollers Switching clock source for LFACLK and LFBCLK is done by setting the LFA and LFB fields in CMU_LFCLKSEL. To ensure no stalls in the Low Energy Peripherals, the clock source should be ready before switching to it. Note To save energy, remember to turn off all oscillators not in use.
Page 102 ...the world's most energy friendly microcontrollers The CMU has built-in HW support to efficiently calibrate the RC oscillators at run-time, see Figure 11.6 (p. 102) The concept is to select a reference and compare the RC frequency with the reference frequency. When the calibration circuit is started, one down-counter running on HFCLK and one up-counter running on a selectable reference clock are started simultaneously.
Page 103: Register Map
...the world's most energy friendly microcontrollers 11.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 CMU_CTRL CMU Control Register 0x004 CMU_HFCORECLKDIV High Frequency Core Clock Division Register 0x008 CMU_HFPERCLKDIV High Frequency Peripheral Clock Division Register 0x00C CMU_HFRCOCTRL HFRCO Control Register...
Page 104: Register Description
...the world's most energy friendly microcontrollers 11.5 Register Description 11.5.1 CMU_CTRL - CMU Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CLKOUTSEL1 Clock Output Select 1 Controls the clock output multiplexer.
Page 105 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description XTAL 32.768 kHz crystal oscillator. BUFEXTCLK An AC coupled buffer is coupled in series with LFXTAL_N pin, suitable for external sinus wave (32.768 kHz). DIGEXTCLK Digital external clock on LFXTAL_N pin. Oscillator is effectively bypassed. 10:9 HFXOTIMEOUT HFXO Timeout...
Page 106 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) HFCORECLKDIV HFCORECLK Divider Specifies the clock divider for HFCORECLK. Value Mode Description HFCLK...
Page 107 ...the world's most energy friendly microcontrollers 11.5.4 CMU_HFRCOCTRL - HFRCO Control Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 16:12 SUDELAY 0x00...
Page 108 ...the world's most energy friendly microcontrollers 11.5.6 CMU_AUXHFRCOCTRL - AUXHFRCO Control Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) TUNING 0x80 AUXHFRCO Tuning Value...
Page 109 ...the world's most energy friendly microcontrollers 11.5.8 CMU_CALCNT - Calibration Counter Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 19:0 CALCNT 0x00000...
Page 110 ...the world's most energy friendly microcontrollers Name Reset Access Description Disables the HFXO. HFXOEN has higher priority if written simultaneously. WARNING: Do not disable the HFRXO if this oscillator is selected as the source for HFCLK. HFXOEN HFXO Enable Enables the HFXO. HFRCODIS HFRCO Disable Disables the HFRCO.
Page 111 ...the world's most energy friendly microcontrollers Name Reset Access Description Clock Select for LFB Selects the clock source for LFBCLK. LFBE Mode Description Disabled LFBCLK is disabled LFRCO LFRCO selected as LFBCLK LFXO LFXO selected as LFBCLK HFCORECLKLEDIV2 HFCORECLK divided by two is selected as LFBCLK ULFRCO ULFRCO selected as LFBCLK...
Page 112 ...the world's most energy friendly microcontrollers Name Reset Access Description LFRCO is enabled and start-up time has exceeded. LFRCOENS LFRCO Enable Status LFRCO is enabled. AUXHFRCORDY AUXHFRCO Ready AUXHFRCO is enabled and start-up time has exceeded. AUXHFRCOENS AUXHFRCO Enable Status AUXHFRCO is enabled.
Page 113 ...the world's most energy friendly microcontrollers 11.5.14 CMU_IFS - Interrupt Flag Set Register Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CALRDY Calibration Ready Interrupt Flag Set Write to 1 to set the Calibration Ready(completed) Interrupt Flag.
Page 114 ...the world's most energy friendly microcontrollers Name Reset Access Description LFRCORDY LFRCO Ready Interrupt Flag Clear Write to 1 to clear the LFRCO Ready Interrupt Flag. HFXORDY HFXO Ready Interrupt Flag Clear Write to 1 to clear the HFXO Ready Interrupt Flag. HFRCORDY HFRCO Ready Interrupt Flag Clear Write to 1 to clear the HFRCO Ready Interrupt Flag.
Page 115 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) External Bus Interface Clock Enable Set to enable the clock for EBI. Low Energy Peripheral Interface Clock Enable Set to enable the clock for LE.
Page 116 ...the world's most energy friendly microcontrollers Name Reset Access Description TIMER0 Timer 0 Clock Enable Set to enable the clock for TIMER0. UART0 Universal Asynchronous Receiver/Transmitter 0 Clock Enable Set to enable the clock for UART0. USART2 Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable Set to enable the clock for USART2.
Page 117 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Description CMU_LFACLKEN0 is ready for update. CMU_LFACLKEN0 is busy synchronizing new value. 11.5.20 CMU_FREEZE - Freeze Register Offset Bit Position 0x054 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 118 ...the world's most energy friendly microcontrollers 11.5.22 CMU_LFBCLKEN0 - Low Frequency B Clock Enable Register 0 (Async Reg) Offset Bit Position 0x060 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) LEUART1 Low Energy UART 1 Clock Enable Set to enable the clock for LEUART1.
Page 119 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description DIV128 LFACLK = LFACLK/128 LETIMER0 DIV256 LFACLK = LFACLK/256 LETIMER0 DIV512 LFACLK = LFACLK/512 LETIMER0 DIV1024 LFACLK = LFACLK/1024 LETIMER0 DIV2048 LFACLK = LFACLK/2048 LETIMER0 DIV4096 LFACLK = LFACLK/4096 LETIMER0 DIV8192...
Page 120 ...the world's most energy friendly microcontrollers Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) LEUART0 Low Energy UART 0 Prescaler Configure Low Energy UART 0 prescaler Value Mode Description...
Page 121 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description PCNT0S0 External pin PCNT0_S0 is clocking PCNT0. PCNT0CLKEN PCNT0 Clock Enable This bit enables/disables the clock to the PCNT. Value Description PCNT0 is disabled. PCNT0 is enabled. 11.5.26 CMU_LCDCTRL - LCD Control Register Offset Bit Position...
Page 122 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) LOCATION I/O Location Decides the location of the CMU I/O pins. Value Mode Description...
Page 123: Wdog - Watchdog Timer
...the world's most energy friendly microcontrollers 12 WDOG - Watchdog Timer Quick Facts What? The WDOG (Watchdog Timer) resets the system in case of a fault condition, and can 0 1 2 3 be enabled in all energy modes as long as the low frequency clock source is available.
Page 124: Wdog Timeout Equation
...the world's most energy friendly microcontrollers 12.3.1 Clock Source Three clock sources are available for use with the watchdog, through the CLKSEL field in WDOG_CTRL. The corresponding clocks must be enabled in the CMU. The SWOSCBLOCK bit in WDOG_CTRL can be written to prevent accidental disabling of the selected clocks.
Page 125: Register Map
...the world's most energy friendly microcontrollers 12.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 WDOG_CTRL Control Register 0x004 WDOG_CMD Command Register 0x008 WDOG_SYNCBUSY Synchronization Busy Register 12.5 Register Description 12.5.1 WDOG_CTRL - Control Register (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p.
Page 126 ...the world's most energy friendly microcontrollers Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) SWOSCBLOCK Software Oscillator Disable Block Set to disallow disabling of the selected WDOG oscillator. Writing this bit to 1 will turn on the selected WDOG oscillator if it is not already running.
Page 127 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CLEAR Watchdog Timer Clear Clear watchdog timer. The bit must be written 4 watchdog cycles before the timeout. Value Mode Description...
Page 128: Prs - Peripheral Reflex System
...the world's most energy friendly microcontrollers 13 PRS - Peripheral Reflex System Quick Facts What? 0 1 2 3 The PRS (Peripheral Reflex System) allows configurable, fast and autonomous communication between the peripherals. Why? Events and signals from one peripheral can be used as input signals or triggers by other peripherals and ensure timing-critical Tim er...
Page 129: Prs Overview
...the world's most energy friendly microcontrollers 13.3.1 Channel Functions Different functions can be applied to a reflex signal within the PRS. Each channel includes an edge detector to enable generation of pulse signals from level signals. It is also possible to generate output reflex signals by configuring the SWPULSE and SWLEVEL bits.
Page 130: Reflex Consumers
...the world's most energy friendly microcontrollers Module Reflex Output Output Format Pin 6 Input Level Pin 7 Input Level Pin 8 Input Level Pin 9 Input Level Pin 10 Input Level Pin 11 Input Level Pin 12 Input Level Pin 13 Input Level Pin 14 Input Level...
Page 131 ...the world's most energy friendly microcontrollers Module Reflex Input Input Format CC1 Input Pulse/Level CC2 Input Pulse/Level DTI Fault Source 0 (TIMER0 only) Pulse DTI Fault Source 1 (TIMER0 only) Pulse DTI Input (TIMER0 only) Pulse/Level UART TX/RX Enable Pulse USART TX/RX Enable Pulse...
Page 132: Register Map
...the world's most energy friendly microcontrollers 13.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 PRS_SWPULSE Software Pulse Register 0x004 PRS_SWLEVEL Software Level Register 0x010 PRS_CH0_CTRL Channel Control Register 0x014 PRS_CH1_CTRL Channel Control Register 0x018...
Page 133 ...the world's most energy friendly microcontrollers 13.5.2 PRS_SWLEVEL - Software Level Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CH7LEVEL Channel 7 Software Level See bit 0.
Page 134 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description POSEDGE A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal NEGEDGE A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal BOTHEDGES A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal...
Page 135 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description 0b001 USART2TXC USART 2 TX complete USART2TXC 0b010 USART2RXDATAV USART 2 RX Data Valid USART2RXDATAV SOURCESEL 0b011100 (TIMER0) 0b000 TIMER0UF Timer 0 Underflow TIMER0UF 0b001 TIMER0OF Timer 0 Overflow TIMER0OF 0b010 TIMER0CC0 Timer 0 Compare/Capture 0 TIMER0CC0...
Page 136: Ebi - External Bus Interface
Quick Facts What? The EBI is used for accessing external parallel devices. The devices appear as a part of the EFM32G's internal memory map 0 1 2 3 and are therefore extremely simple to use. Why? Even though the EFM32G is versatile, there might be a need for specific external devices such as extra RAM, FLASH, LCD.
Page 137: Ebi Non-Multiplexed 8-Bit Data, 8-Bit Address Read Operation
...the world's most energy friendly microcontrollers multiplexed modes. Also for the non-multiplexed 8-bit address mode both the address and data fit into these 16 EBI_AD pins. If more address bits or data bits are needed, external latches can be used to support up to 24-bit addresses or 16-bit data in the multiplexed addressing modes using only the 16 EBI_AD pins.
Page 138: Ebi Multiplexed 16-Bit Data, 16-Bit Address Read Operation
...the world's most energy friendly microcontrollers the LSB of the address driven into the EBI_AD bus, i.e. the EBI_AD[0]-bit, corresponds to the second least significant bit of the address, i.e. ADDR[1]. At the external device, the LSB of the address must be tied either low or high in order to create a full address. Figure 14.3.
Page 139: Ebi Multiplexed 8-Bit Data, 24-Bit Address Read Operation
...the world's most energy friendly microcontrollers by programming the MODE field in the EBI_CTRL register to D8A24ALE. Read and write signals are shown in Figure 14.6 (p. 139) and Figure 14.7 (p. 139) respectively. Figure 14.6. EBI Multiplexed 8-bit Data, 24-bit Address Read Operation ADDRSETUP RDSETUP RDSTRB...
Page 140 ...the world's most energy friendly microcontrollers Figure 14.8. EBI Default Memory Map (ALTMAP = 0) 0 xffffffff 0 xc0 0 0 0 0 0 0 0 xbfffffff 0 x8 fffffff EBI Region 3 (64 MB) 0 x8 c0 0 0 0 0 0 0 x8 bffffff EBI Regions EBI Region 2 (64 MB)
Page 141 14.3.8 Control Signal Polarity 14.3.9 Pin Configuration In order to give the EBI access to the external pins of the EFM32G, the GPIO must be configured accordingly. The lines must be set to Push-Pull, which is described in detail in the GPIO section.
Page 142 ...the world's most energy friendly microcontrollers EBI_ALE pin is enabled by the ALEPEN bit , and the EBI_ARDY pin is enabled by the ARDYPEN bit of the EBI_ROUTE register. www.silabs.com 2014-07-02 - Gecko Family - d0001_Rev1.30...
Page 143: Register Map
...the world's most energy friendly microcontrollers 14.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 EBI_CTRL Control Register 0x004 EBI_ADDRTIMING Address Timing Register 0x008 EBI_RDTIMING Read Timing Register 0x00C EBI_WRTIMING Write Timing Register 0x010 EBI_POLARITY...
Page 144: Register Description
...the world's most energy friendly microcontrollers Offset Name Type Description 0x0A0 EBI_IFC Interrupt Flag Clear Register 0x0A4 EBI_IEN Interrupt Enable Register 14.5 Register Description 14.5.1 EBI_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description ALTMAP Alternative Address Map Enable This field enables or disables the alternative (256 MB per bank) address map.
Page 145 ...the world's most energy friendly microcontrollers Name Reset Access Description NOIDLE3 No idle cycle insertion on bank 3. Enables or disables idle state insertion between transfers for bank 3. Ignored when ITS = 0. NOIDLE2 No idle cycle insertion on bank 2. Enables or disables idle state insertion between transfers for bank 2.
Page 146 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description D8A8 EBI_AD drives 8 bit data, 8 bit address, ALE not used. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register. D16A16ALE EBI_AD drives 16 bit data, 16 bit address, ALE is used for address latching. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register.
Page 147 ...the world's most energy friendly microcontrollers Name Reset Access Description Enables or disables page mode reads. PREFETCH Prefetch Enable Enables or disables prefetching of data from sequential address. HALFRE Half Cycle REn Strobe Duration Enable Enables or disables half cycle duration of the REn strobe in the last RDSTRB cycle. 27:18 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 148 ...the world's most energy friendly microcontrollers 14.5.5 EBI_POLARITY - Polarity Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) BLPOL BL Polarity Sets the polarity of the EBI_BLn lines.
Page 149 ...the world's most energy friendly microcontrollers 14.5.6 EBI_ROUTE - I/O Routing Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 30:28 LOCATION I/O Location...
Page 150 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description EBI_A[26:L] pins enabled. EBI_A[27:L] pins enabled. 17:16 Sets the lower bound for EBI_A enabling Sets the lower bound of the EBI_A lines which can be enabled in the APEN field. Value Mode Description...
Page 151 ...the world's most energy friendly microcontrollers Name Reset Access Description ADDRHOLD Address Hold Time Sets the number of cycles the address is held after ALE is asserted. Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) ADDRSETUP Address Setup Time Sets the number of cycles the address is driven onto the ADDRDAT bus before ALE is asserted.
Page 152 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) WBUFDIS Write Buffer Disable Enables or disables the write buffer. HALFWE Half Cycle WEn Strobe Duration Enable Enables or disables half cycle duration of the WEn strobe in the last WRSTRB cycle.
Page 153 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description ACTIVELOW WEn and NANDWEn are active low. ACTIVEHIGH WEn and NANDWEn are active high. REPOL Read Enable Polarity Sets the polarity of the EBI_REn and EBI_NANDREn lines. Value Mode Description...
Page 154 ...the world's most energy friendly microcontrollers Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) PAGEMODE Page Mode Access Enable Enables or disables page mode reads. PREFETCH Prefetch Enable Enables or disables prefetching of data from sequential address.
Page 155 ...the world's most energy friendly microcontrollers 14.5.14 EBI_POLARITY2 - Polarity Register 2 Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) BLPOL BL Polarity Sets the polarity of the EBI_BLn lines.
Page 156 ...the world's most energy friendly microcontrollers 14.5.15 EBI_ADDRTIMING3 - Address Timing Register 3 Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:29 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) HALFALE Half Cycle ALE Strobe Duration Enable Enables or disables half cycle duration of the ALE strobe in the last address setup cycle.
Page 157 ...the world's most energy friendly microcontrollers Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) RDSETUP Read Setup Time Sets the number of cycles the address setup before REn is asserted. 14.5.17 EBI_WRTIMING3 - Write Timing Register 3 Offset Bit Position...
Page 158 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description ACTIVELOW BLn[1:0] are active low. ACTIVEHIGH BLn[1:0] are active high. ARDYPOL ARDY Polarity Sets the polarity of the EBI_ARDY line. Value Mode Description ACTIVELOW ARDY is active low. ACTIVEHIGH ARDY is active high.
Page 159 ...the world's most energy friendly microcontrollers Name Reset Access Description Sets the number of cycles needed for intrapage page access time. If set to 0, 1 cycle is inserted by HW. Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) INCHIT Intrapage hit only on incremental addresses Sets whether page hits occur on any member in a page or only on incremental addresses.
Page 160 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) ECCCLEAR Error Correction Code Clear Write to 1 to clear ECCPARITY. ECCSTOP Error Correction Code Generation Stop Write to 1 to stop ECC generation.
Page 161 ...the world's most energy friendly microcontrollers 14.5.23 EBI_ECCPARITY - ECC Parity register Offset Bit Position 0x058 Reset Access Name Name Reset Access Description 31:0 ECCPARITY 0x00000000 ECC Parity Data ECC Parity Data. 14.5.24 EBI_TFTCTRL - TFT Control Register Offset Bit Position 0x05C Reset Access...
Page 162 ...the world's most energy friendly microcontrollers Name Reset Access Description WIDTH TFT Transaction Width This field sets TFT tranaction width. Value Mode Description BYTE TFT Data is 8 bit wide. HALFWORD TFT Data is 16 bit wide. 15:13 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) COLOR1SRC Masking/Alpha Blending Color1 Source This field sets the Masking/Alpha Blending Color1 Source.
Page 163 ...the world's most energy friendly microcontrollers 14.5.25 EBI_TFTSTATUS - TFT Status Register Offset Bit Position 0x060 Reset Access Name Name Reset Access Description 31:27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 26:16 VCNT 0x000...
Page 164 ...the world's most energy friendly microcontrollers 14.5.27 EBI_TFTSTRIDE - TFT Stride Register Offset Bit Position 0x068 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 11:0 HSTRIDE 0x000...
Page 165 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 29:28 HSYNCSTART HSYNC Start Delay Sets the HSYNC start position into the horizontal back porch in DCLK cycles. 27:26 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 166 ...the world's most energy friendly microcontrollers 14.5.31 EBI_TFTTIMING - TFT Timing Register Offset Bit Position 0x078 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 29:28 TFTHOLD TFT Hold Time...
Page 167 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description ACTIVEHIGH HSYNC is active high. DATAENPOL TFT DATAEN Polarity Sets the polarity of the EBI_DATAEN line. Value Mode Description ACTIVELOW DATAEN is active low. ACTIVEHIGH DATAEN is active high. DCLKPOL TFT DCLK Polarity Sets the active edge polarity of the EBI_DCLK line.
Page 168 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) ALPHA 0x000 TFT Alpha Blending Factor Sets the alpha blending factor. The maximum value is 256. 14.5.35 EBI_TFTPIXEL0 - TFT Pixel 0 Register Offset Bit Position...
Page 169 ...the world's most energy friendly microcontrollers 14.5.37 EBI_TFTPIXEL - TFT Alpha Blending Result Pixel Register Offset Bit Position 0x090 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 DATA 0x0000...
Page 170 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) DDJIT Direct Drive Jitter Interrupt Flag Set when DCLKPERIOD is not met. DDEMPTY Direct Drive Data Empty Interrupt Flag Set when Direct Drive engine EBI_TFTDD data is empty.
Page 171 ...the world's most energy friendly microcontrollers 14.5.41 EBI_IFC - Interrupt Flag Clear Register Offset Bit Position 0x0A0 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) DDJIT Direct Drive Jitter Interrupt Flag Clear Write to 1 to clear Direct Drive Jitter Interrupt flag.
Page 172 ...the world's most energy friendly microcontrollers Name Reset Access Description Set to enable interrupt on Horizontal Sync interrupt flag. VSYNC Vertical Sync Interrupt Enable Set to enable interrupt on Vertical Sync interrupt flag. www.silabs.com 2014-07-02 - Gecko Family - d0001_Rev1.30...
Page 173: C - Inter-Integrated Circuit Interface
...the world's most energy friendly microcontrollers 15 I C - Inter-Integrated Circuit Interface Quick Facts What? 0 1 2 3 The I C interface allows communication on I C-buses with the lowest energy consumption possible. Why? EFM32 C m aster/ slave C is a popular serial bus that enables communication with a number of external devices using only two I/O pins.
Page 174: Functional Description
...the world's most energy friendly microcontrollers 15.3 Functional Description An overview of the I C module is shown in Figure 15.1 (p. 174) . Figure 15.1. I C Overview Peripheral Bus C Control and Transm it Buffer Receive Buffer Status I2Cn_SDA Sym bol Transm it...
Page 175: C Start And Stop Conditions
...the world's most energy friendly microcontrollers Note If V drops below the voltage on SCL and SDA lines, the MCU could become back powered and pull the SCL and SDA lines low. 15.3.1.1 START and STOP Conditions START and STOP conditions are used to initiate and stop transactions on the I C-bus.
Page 176: C Reserved I C Addresses
...the world's most energy friendly microcontrollers on the bus can try to gain control of it. If the current master wishes to make another transfer immediately after the current, it can start a new transfer directly by transmitting a repeated START condition (Sr) instead of a STOP followed by a START.
Page 177 ...the world's most energy friendly microcontrollers 15.3.1.4 10-bit Addressing To address a slave using a 10-bit address, two bytes are required to specify the address instead of one. The seven first bits of the first byte must then be 1111 0XX, where XX are the two most significant bits of the 10-bit address.
Page 178: C High And Low Periods For Low Clkdiv
...the world's most energy friendly microcontrollers 15.3.3 Safely Disabling and Changing Slave Configuration The I C slave is partially asynchronous, and some precautions are necessary to always ensure a safe slave disable or slave configuration change. These measures should be taken, if (while the slave is enabled) the user cannot guarantee that an address match will not occur at the exact time of slave disable or slave configuration change.
Page 179: C Clock Mode
...the world's most energy friendly microcontrollers Table 15.3. I C Clock Mode HFPERCLK Clock Low High Sm max frequency Fm max frequency Fm+ max frequency frequency (MHz) Ratio (CLHR) (kHz) (kHz) (kHz) 1000 1000 1000 15.3.5 Arbitration Arbitration is enabled by default, but can be disabled by setting the ARBDIS bit in I2Cn_CTRL. When arbitration is enabled, the value on SDA is sensed every time the I C module attempts to change its value.
Page 180 ...the world's most energy friendly microcontrollers transmit shift register is empty and ready for new data, the byte from the transmit buffer is then loaded into the shift register. The byte is then kept in the shift register until it is transmitted. When a byte has been transmitted, a new byte is loaded into the shift register (if available in the transmit buffer).
Page 181: C Master State Machine
...the world's most energy friendly microcontrollers After the address has been transmitted, a sequence of bytes can be read from or written to the slave, depending on the value of the R/W bit (bit 0 in the address byte). If the bit was cleared, the master has entered a master transmitter role, where it now transmits data to the slave.
Page 182: C Interactions In Prioritized Order
...the world's most energy friendly microcontrollers 15.3.7.2 Interactions Whenever the I C module is waiting for interaction from software, it holds the bus clock SCL low, freezing all bus activities, and the BUSHOLD interrupt flag in I2Cn_IF is set. The action(s) required by software depends on the current state the of the I C module.
Page 183 ...the world's most energy friendly microcontrollers set in a pending state, which can be read from the STATUS register. A pending START command can for instance be identified by PSTART having a high value. Whenever the I C module requires an interaction, it checks the pending commands. If one or a combination of these can fulfill an interaction, they are consumed by the module and the transmission continues without setting the BUSHOLD interrupt flag in I2Cn_IF to get an interaction from software.
Page 184: C Master Transmitter
...the world's most energy friendly microcontrollers value of I2Cn_STATE will then be 0x57. As seen in the table, the I C module also stops in this state if the address is not available after a repeated start condition. To continue, write a byte to I2Cn_TXDATA with the address of the slave in the 7 most significant bits and the least significant bit cleared (ADDR+W).
Page 185 ...the world's most energy friendly microcontrollers I2Cn_STATE Description I2Cn_IF Required Response interaction START Repeated start condition will be sent STOP + STOP will be sent and the bus released. Then START a START will be sent when the bus becomes idle Data transmitted TXBL interrupt flag...
Page 186: C Master Receiver
...the world's most energy friendly microcontrollers As when operating as a master transmitter, arbitration can be lost as a master receiver. When this happens the ARBLOST interrupt flag in I2Cn_IF is set, and the master has a possibility of being selected as a slave given the correct conditions.
Page 187: C State Values
...the world's most energy friendly microcontrollers I2Cn_STATE Description I2Cn_IF Required Response interaction START START will be sent when bus becomes idle Arbitration lost ARBLOST interrupt None flag START START will be sent when bus becomes idle 15.3.8 Bus States The I2Cn_STATE register can be used to determine which state the I C module and the I C bus are in at a given time.
Page 188: C Slave State Machine
...the world's most energy friendly microcontrollers 15.3.9.1 Slave State Machine The slave state machine is shown in Figure 15.11 (p. 188) . The dotted lines show where I C-specific interrupt flags are set. The full-drawn circles show places where interaction may be required by software to let the transmission proceed.
Page 189 ...the world's most energy friendly microcontrollers 15.3.9.3 Slave Transmitter When SLAVE in I2Cn_CTRL is set, the RSTART interrupt flag in I2Cn_IF will be set when repeated START conditions are detected. After a START or repeated START condition, the bus master will transmit an address along with an R/W bit.
Page 190: C Slave Transmitter
...the world's most energy friendly microcontrollers Table 15.9. I C Slave Transmitter I2Cn_STATE Description I2Cn_IF Required Response interaction 0x41 Repeated START RSTART interrupt flag RXDATA Receive and compare address received (BUSHOLD interrupt flag) 0x75 ADDR + R received ADDR interrupt flag ACK + ACK will be sent, then DATA TXDATA...
Page 191: C - Slave Receiver
...the world's most energy friendly microcontrollers See Table 15.10 (p. 191) for more information. Table 15.10. I C - Slave Receiver I2Cn_STATE Description I2Cn_IF Required Response interaction Repeated START RSTART interrupt flag RXDATA Receive and compare address received (BUSHOLD interrupt flag) 0x71 ADDR + W received...
Page 192: C Bus Error Response
...the world's most energy friendly microcontrollers 15.3.11 Using 10-bit Addresses When using 10-bit addresses in slave mode, set the I2Cn_SADDR register to 1111 0XX where XX are the two most significant bits of the 10-bit address, and set I2Cn_SADDRMASK to 0xFF. Address matches will now be given on all 10-bit addresses where the two most significant bits are correct.
Page 193 ...the world's most energy friendly microcontrollers Many slave-only devices operating on an I C-bus are not capable of driving SCL low, but in the rare case that SCL is stuck LOW, the advice is to apply a hardware reset signal to the slaves on the bus. If this does not work, cycle the power to the devices in order to make them release SCL.
Page 194 ...the world's most energy friendly microcontrollers • Transmit buffer and shift register empty. No data to send • Transmit buffer empty 15.3.14 Interrupts The interrupts generated by the I C module are combined into one interrupt vector, I2C_INT. If I interrupts are enabled, an interrupt will be made if one or more of the interrupt flags in I2Cn_IF and their corresponding bits in I2Cn_IEN are set.
Page 195: Register Map
...the world's most energy friendly microcontrollers 15.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 I2Cn_CTRL Control Register 0x004 I2Cn_CMD Command Register 0x008 I2Cn_STATE State Register 0x00C I2Cn_STATUS Status Register 0x010 I2Cn_CLKDIV Clock Division Register...
Page 196 ...the world's most energy friendly microcontrollers Name Reset Access Description When set, the bus automatically goes idle on a bus idle timeout, allowing new transfers to be initiated. Value Description A bus idle timeout has no effect on the bus state. A bus idle timeout tells the I C module that the bus is idle, allowing new transfers to be initiated.
Page 197 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Description Software must give one ACK command for each ACK transmitted on the I C bus. Addresses that are not automatically NACK'ed, and all data is automatically acknowledged. SLAVE Addressable as Slave Set this bit to allow the device to be selected as an I C slave.
Page 198 ...the world's most energy friendly microcontrollers 15.5.3 I2Cn_STATE - State Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) STATE Transmission State The state of any current transmission.
Page 199 ...the world's most energy friendly microcontrollers Name Reset Access Description RXDATAV RX Data Valid Set when data is available in the receive buffer. Cleared when the receive buffer is empty. TXBL TX Buffer Level Indicates the level of the transmit buffer. Set when the transmit buffer is empty, and cleared when it is full. TX Complete Set when a transmission has completed and no more data is available in the transmit buffer.
Page 200 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) ADDR 0x00 Slave address Specifies the slave address of the device. Reserved To ensure compatibility with future devices, always write bits to 0.
Page 201 ...the world's most energy friendly microcontrollers 15.5.9 I2Cn_RXDATAP - Receive Buffer Data Peek Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) RXDATAP 0x00 RX Data Peek...
Page 202 ...the world's most energy friendly microcontrollers Name Reset Access Description Set on each clock low timeout. The timeout value can be set in CLTO bit field in the I2Cn_CTRL register. BITO Bus Idle Timeout Interrupt Flag Set on each bus idle timeout. The timeout value can be set in the BITO bit field in the I2Cn_CTRL register. RXUF Receive Buffer Underflow Interrupt Flag Set when data is read from the receive buffer through the I2Cn_RXDATA register while the receive buffer is empty.
Page 203 ...the world's most energy friendly microcontrollers Name Reset Access Description SSTOP Set SSTOP Interrupt Flag Write to 1 to set the SSTOP interrupt flag. CLTO Set Clock Low Interrupt Flag Write to 1 to set the CLTO interrupt flag. BITO Set Bus Idle Timeout Interrupt Flag Write to 1 to set the BITO interrupt flag.
Page 204 ...the world's most energy friendly microcontrollers Name Reset Access Description Write to 1 to clear the SSTOP interrupt flag. CLTO Clear Clock Low Interrupt Flag Write to 1 to clear the CLTO interrupt flag. BITO Clear Bus Idle Timeout Interrupt Flag Write to 1 to clear the BITO interrupt flag.
Page 205 ...the world's most energy friendly microcontrollers Name Reset Access Description CLTO Clock Low Interrupt Enable Enable interrupt on clock low timeout. BITO Bus Idle Timeout Interrupt Enable Enable interrupt on bus idle timeout. RXUF Receive Buffer Underflow Interrupt Enable Enable interrupt on receive buffer underflow. TXOF Transmit Buffer Overflow Interrupt Enable Enable interrupt on transmit buffer overflow.
Page 206 ...the world's most energy friendly microcontrollers Name Reset Access Description LOCATION I/O Location Decides the location of the I C I/O pins. Value Mode Description LOC0 Location 0 LOC1 Location 1 LOC2 Location 2 LOC3 Location 3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) SCLPEN SCL Pin Enable When set, the SCL pin of the I...
Page 207: Usart - Universal Synchronous Asynchronous Receiver/Transmitter
...the world's most energy friendly microcontrollers 16 USART - Universal Synchronous Asynchronous Receiver/Transmitter Quick Facts What? 0 1 2 3 The USART handles high-speed UART, SPI- bus, SmartCards, and IrDA communication. Why? Serial communication is frequently used in embedded systems and the USART allows controller efficient communication with a wide range of external devices.
Page 208: Functional Description
...the world's most energy friendly microcontrollers • Configurable number of data bits, 4-16 (plus the parity bit, if enabled) • HW parity bit generation and check • Configurable number of stop bits in asynchronous mode: 0.5, 1, 1.5, 2 • HW collision detection •...
Page 209: Usart Asynchronous Frame Format
...the world's most energy friendly microcontrollers Asynchronous or synchronous mode can be selected by configuring SYNC in USARTn_CTRL. The options are listed with supported protocols in Table 16.1 (p. 209) . Full duplex and half duplex communication is supported in both asynchronous and synchronous mode. Table 16.1.
Page 210: Usart Data Bits
...the world's most energy friendly microcontrollers Table 16.3. USART Data Bits DATA BITS [3:0] Number of Data bits 0001 0010 0011 0100 0101 8 (Default) 0110 0111 1000 1001 1010 1011 1100 1101 Table 16.4. USART Stop Bits STOP BITS [1:0] Number of Stop bits 1 (Default) The order in which the data bits are transmitted and received is defined by MSBF in USARTn_CTRL.
Page 211: Usart Parity Bits
...the world's most energy friendly microcontrollers Table 16.5. USART Parity Bits STOP BITS [1:0] Description No parity bit (Default) Reserved Even parity Odd parity 16.3.2.2 Clock Generation The USART clock defines the transmission and reception data rate. When operating in asynchronous mode, the baud rate (bit-rate) is given by Equation 16.1 (p.
Page 212: Usart Baud Rates @ 4Mhz Peripheral Clock
...the world's most energy friendly microcontrollers Table 16.7. USART Baud Rates @ 4MHz Peripheral Clock USARTn_OVS =00 USARTn_OVS =01 Desired baud rate Actual baud Actual baud USARTn_CLKDIV/256 Error % USARTn_CLKDIV/256 Error % [baud/s] rate [baud/s] rate [baud/s] 415,75 599,88 -0,02 832,25 600,06 0,01...
Page 213 ...the world's most energy friendly microcontrollers frames, complete with control bits to be written at once. When data is written to the transmit buffer using USARTn_TXDATAX and USARTn_TXDOUBLEX, the 9th bit(s) written to these registers override the value in BIT8DV in USARTn_CTRL, and alone define the 9th bits that are transmitted if 9-bit frames are used.
Page 214 ...the world's most energy friendly microcontrollers • Tristate transmitter after transmission: If TXTRIAT is set, TXTRI is set after the frame has been fully transmitted, tristating the transmitter output. Tristating of the output can also be performed automatically by setting AUTOTRI. If AUTOTRI is set TXTRI is always read as 0. Note When in SmartCard mode with repeat enabled, none of the actions, except generate break, will be performed until the frame is transmitted without failure.
Page 215 ...the world's most energy friendly microcontrollers The basic operation of the receive buffer when DATABITS in USARTn_FRAME is configured to less than 10 bits is shown in Figure 16.4 (p. 215) . Figure 16.4. USART Receive Buffer Operation Peripheral Bus RXDOUBLE RXDATA, RXDOUBLEX...
Page 216: Usart Sampling Of Start And Data Bits
...the world's most energy friendly microcontrollers When a high-to-low transition is registered on the input while the receiver is idle, this is recognized as a start-bit, and the baud rate generator is synchronized with the incoming frame. For oversampling modes 16, 8 and 6, every bit in the incoming frame is sampled three times to gain a level of noise immunity.
Page 217: Usart Sampling Of Stop Bits When Number Of Stop Bits Are 1 Or More
...the world's most energy friendly microcontrollers Figure 16.6. USART Sampling of Stop Bits when Number of Stop Bits are 1 or More n’th bit 1 stop bit Idle or start bit 13 14 15 16 1 9 10 0/ 1 0/ 1 0/ 1 0/ 1...
Page 218 ...the world's most energy friendly microcontrollers can receive the data it transmits, but it is also used to allow the USART to read and write to the same pin, which is required for some half duplex communication modes. In this mode, the U(S)n_TX pin must be enabled as an output in the GPIO.
Page 219 ...the world's most energy friendly microcontrollers This can be done manually by assigning a GPIO to turn the driver on or off, or it can be handled automatically by the USART. If AUTOCS in USARTn_CTRL is set, the USn_CS output is automatically activated one baud period before the transmitter starts transmitting data, and deactivated when the last bit has been transmitted and there is no more data in the transmit buffer to transmit, or the transmitter becomes disabled.
Page 220: Usart Transmission Of Large Frames
...the world's most energy friendly microcontrollers Figure 16.9. USART Transmission of Large Frames Peripheral Bus TX buffer elem ent 1 Write CTRL TX buffer elem ent 0 Write CTRL Shift register Write CTRL As shown in Figure 16.9 (p. 220) , frame transmission control bits are taken from the second element in FIFO.
Page 221 ...the world's most energy friendly microcontrollers Figure 16.11. USART Reception of Large Frames Peripheral Bus RX buffer elem ent 0 Status RX buffer elem ent 1 Status Shift register Status The two buffer elements can be read at the same time using the USARTn_RXDOUBLE or USARTn_RXDOUBLEX register.
Page 222: Usart Iso 7816 Data Frame Without Error
...the world's most energy friendly microcontrollers BIT8DV in USARTn_CTRL can be used to specify the value of the 9th bit without writing to the transmit buffer with USARTn_TXDATAX or USARTn_TXDOUBLEX, giving higher efficiency in multi-processor mode, as the 9th bit is only set when writing address frames, and 8-bit writes to the USART can be used when writing the data frames.
Page 223: Usart Iso 7816 Data Frame With Error
...the world's most energy friendly microcontrollers Figure 16.13. USART ISO 7816 Data Frame With Error ISO 7816 Fram e with error Start or idle Stop or idle Stop Stop On a parity error, the NAK is generated by hardware. The NAK generated by the receiver is sampled as the stop-bit of the frame.
Page 224: Usart Spi Modes
...the world's most energy friendly microcontrollers 16.3.3.1 Frame Format The frames used in synchronous mode need no start and stop bits since a single clock is available to all parts participating in the communication. Parity bits cannot be used in synchronous mode. The USART supports frame lengths of 4 to 16 bits per frame.
Page 225 ...the world's most energy friendly microcontrollers Figure 16.15. USART SPI Timing CLKPOL = 0 USn_CLK CLKPOL = 1 USn_CS CLKPHA = 0 USn_TX/ USn_RX CLKPHA = 1 If CPHA=1, the TX underflow flag, TXUF, will be set on the first setup clock edge of a frame in slave mode if TX data is not available.
Page 226 ...the world's most energy friendly microcontrollers The output and input to the USART are also swapped when in slave mode, making the receiver take its input from USn_TX (MOSI) and the transmitter drive USn_RX (MISO). To transmit data when in slave mode, the slave must load data into the transmit buffer and enable the transmitter.
Page 227 ...the world's most energy friendly microcontrollers • Transmit buffer has room for more data. Even though there are two sources for write requests to the DMA, only one should be used at a time, since the requests from both sources are cleared even though only one of the requests are used. In some cases, it may be sensible to temporarily stop DMA access to the USART when an error such as a framing error has occurred.
Page 228: Usart Irda Pulse Widths
...the world's most energy friendly microcontrollers and modulates it before it leaves USART0. In the same way, the input signal is demodulated before it enters the actual USART module. The modulator is only available on USART0, and implements the original Rev. 1.0 physical layer and one high speed extension which supports speeds from 2.4 kbps to 1.152 Mbps.
Page 229: Register Map
...the world's most energy friendly microcontrollers 16.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 USARTn_CTRL Control Register 0x004 USARTn_FRAME USART Frame Format Register 0x008 USARTn_TRIGCTRL USART Trigger Control register 0x00C USARTn_CMD Command Register...
Page 230 ...the world's most energy friendly microcontrollers Name Reset Access Description 27:26 TXDELAY TX Delay Transmission Configurable delay before new transfers. Frames sent back-to-back are not delayed. Value Mode Description NONE Frames are transmitted immediately SINGLE Transmission of new frames are delayed by a single baud period DOUBLE Transmission of new frames are delayed by two baud periods TRIPLE...
Page 231 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Description Output from the transmitter is passed unchanged to U(S)n_TX Output from the transmitter is inverted before it is passed to U(S)n_TX RXINV Receiver Input Invert Setting this bit will invert the input to the USART receiver. Value Description Input is passed directly to the receiver...
Page 232 ...the world's most energy friendly microcontrollers Name Reset Access Description Multi-processor mode uses the 9th bit of the USART frames to tell whether the frame is an address frame or a data frame. Value Description The 9th bit of incoming frames has no special function An incoming frame with the 9th bit equal to MPAB will be loaded into the receive buffer regardless of RXBLOCK and will result in the MPAB interrupt flag being set CCEN...
Page 233 ...the world's most energy friendly microcontrollers Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) DATABITS Data-Bit Mode This register sets the number of data bits in a USART frame. Value Mode Description...
Page 234 ...the world's most energy friendly microcontrollers 16.5.4 USARTn_CMD - Command Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CLEARRX Clear RX Set to clear receive buffer and the RX shift register.
Page 235 ...the world's most energy friendly microcontrollers 16.5.5 USARTn_STATUS - USART Status Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) RXFULL RX FIFO Full Set when the RXFIFO is full.
Page 236 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:21 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 20:6 0x0000 Fractional Clock Divider Specifies the fractional clock divider for the USART. Reserved To ensure compatibility with future devices, always write bits to 0.
Page 237 ...the world's most energy friendly microcontrollers 16.5.9 USARTn_RXDOUBLEX - RX Buffer Double Data Extended Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description FERR1 Data Framing Error 1 Set if data in buffer has a framing error. Can be the result of a break condition. PERR1 Data Parity Error 1 Set if data in buffer has a parity error (asynchronous mode only).
Page 238 ...the world's most energy friendly microcontrollers 16.5.11 USARTn_RXDATAXP - RX Buffer Data Extended Peek Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) FERRP Data Framing Error Peek Set if data in buffer has a framing error.
Page 239 ...the world's most energy friendly microcontrollers Name Reset Access Description Set if data in buffer has a parity error (asynchronous mode only). 13:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) RXDATAP0 0x000 RX Data 0 Peek...
Page 240 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) TXDATA 0x00 TX Data This frame will be added to TX buffer. Only 8 LSB can be written using this register. 9th bit and control bits will be cleared. 16.5.15 USARTn_TXDOUBLEX - TX Buffer Double Data Extended Register Offset Bit Position...
Page 241 ...the world's most energy friendly microcontrollers 16.5.16 USARTn_TXDOUBLE - TX Buffer Double Data Register Offset Bit Position 0x03C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:8 TXDATA1 0x00...
Page 242 ...the world's most energy friendly microcontrollers Name Reset Access Description Set when data is incoming while the receive shift register is full. The data previously in the shift register is lost. RXFULL RX Buffer Full Interrupt Flag Set when the receive buffer becomes full. RXDATAV RX Data Valid Interrupt Flag Set when data becomes available in the receive buffer.
Page 243 ...the world's most energy friendly microcontrollers 16.5.19 USARTn_IFC - Interrupt Flag Clear Register Offset Bit Position 0x048 Reset Access Name Name Reset Access Description 31:13 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) Clear Collision Check Fail Interrupt Flag Write to 1 to clear the CCF interrupt flag.
Page 244 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:13 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) Collision Check Fail Interrupt Enable Enable interrupt on collision check error detected. Slave-Select In Master Mode Interrupt Enable Enable interrupt on slave-select in master mode.
Page 245 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description PRSCH0 PRS Channel 0 selected PRSCH1 PRS Channel 1 selected PRSCH2 PRS Channel 2 selected PRSCH3 PRS Channel 3 selected PRSCH4 PRS Channel 4 selected PRSCH5 PRS Channel 5 selected PRSCH6 PRS Channel 6 selected PRSCH7...
Page 246 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Description The USn_CLK pin is enabled CSPEN CS Pin Enable When set, the CS pin of the USART is enabled. Value Description The USn_CS pin is disabled The USn_CS pin is enabled TXPEN TX Pin Enable When set, the TX/MOSI pin of the USART is enabled...
Page 247: Uart - Universal Asynchronous Receiver/Transmitter
...the world's most energy friendly microcontrollers 17 UART - Universal Asynchronous Receiver/ Transmitter Quick Facts What? 0 1 2 3 The UART is capable of high-speed asynchronous serial communication. Why? Serial communication is frequently used in embedded systems and the UART allows efficient communication with a wide range of controller external devices.
Page 248: Functional Description
...the world's most energy friendly microcontrollers • Communication debugging • PRS can trigger transmissions • Full DMA support 17.3 Functional Description The UART is functionally equivalent to the USART with the exceptions defined in Table 17.1 (p. 248) . The register map and register descriptions are equal to those of the USART. See the USART chapter for detailed information on the operation of the UART.
Page 249: Leuart - Low Energy Universal Asynchronous Receiver/Transmitter
...the world's most energy friendly microcontrollers 18 LEUART - Low Energy Universal Asynchronous Receiver/Transmitter Quick Facts What? The LEUART provides full UART communication using a low frequency 32.768 0 1 2 3 kHz clock, and has special features for communication without CPU intervention. Why? It allows UART communication to be controller...
Page 250: Functional Description
...the world's most energy friendly microcontrollers • Can use a high frequency clock source for even higher baud rates • Configurable number of data bits: 8 or 9 (plus parity bit, if enabled) • Configurable parity: off, even or odd •...
Page 251: Leuart Parity Bit
...the world's most energy friendly microcontrollers a parity bit is inserted to make the number of high bits (data + parity) even. If odd parity is chosen, the parity bit makes the total number of high bits odd. When parity bits are disabled, which is the default configuration, the parity bit is omitted.
Page 252: Leuart Baud Rates
...the world's most energy friendly microcontrollers Table 18.2. LEUART Baud Rates Desired baud rate LEUARTn_CLKDIV LEUARTn_CLKDIV/256 Actual baud rate Error [%] [baud/s] [baud/s] 27704 108,21875 300,0217 0,01 13728 53,625 599,8719 -0,02 1200 6736 26,3125 1199,744 -0,02 2400 3240 12,65625 2399,487 -0,02 4800 1488...
Page 253 ...the world's most energy friendly microcontrollers Figure 18.3. LEUART Transmitter Overview TXDATA BIT8DV TXENS Transm it shift register LEUn_TX d0- d8 control control Transm it buffer TXDATAX 18.3.4.2 Frame Transmission Control The transmission control bits, which can be written using LEUARTn_TXDATAX, affect the transmission of the written frame.
Page 254 ...the world's most energy friendly microcontrollers receive buffer is full, the received frame remains in the shift register until more space in the receive buffer is available. If an incoming frame is detected while both the receive buffer and the receive shift register are full, the data in the receive shift register is overwritten, and the RXOF interrupt flag in LEUARTn_IF is set to indicate the buffer overflow.
Page 255: Leuart Optimal Sampling Point
...the world's most energy friendly microcontrollers incoming frames without passing the frames to software by loading them into the receive buffer. This is accomplished by blocking incoming data. Incoming data is blocked as long as RXBLOCK in LEUARTn_STATUS is set. When blocked, frames received by the receiver will not be loaded into the receive buffer, and software is not notified by the RXDATAV bit in LEUARTn_STATUS or the RXDATAV interrupt flag in LEUARTn_IF at their arrival.
Page 256 ...the world's most energy friendly microcontrollers PERR can be accessed by reading the frame from the receive buffer using the LEUARTn_RXDATAX register. 18.3.5.5 Framing Error and Break Detection A framing error is the result of a received frame where the stop bit was sampled to a value of 0. This can be the result of noise and baud rate errors, but can also be the result of a break generated by the transmitter on purpose.
Page 257 ...the world's most energy friendly microcontrollers 18.3.5.8 Multi-Processor Mode To simplify communication between multiple processors and maintain compatibility with the USART, the LEUART supports a multi-processor mode. In this mode the 9th data bit in each frame is used to indicate whether the content of the remaining 8 bits is data or an address.
Page 258 ...the world's most energy friendly microcontrollers When communicating over a single data-link, the transmitter must thus be tristated whenever not transmitting data. If AUTOTRI in LEUARTn_CTRL is set, the LEUART automatically tristates LEUn_TX whenever the transmitter is inactive. It is then the responsibility of the software protocol to make sure the transmitter is not transmitting data whenever incoming data is expected.
Page 259 ...the world's most energy friendly microcontrollers byte transfers and 9 bit data + control/status bits transfers both to and from the LEUART. The DMA will start up the HFRCO and run from this when it is waken by the LEUART in EM2. The HFRCO is disabled once the transaction is done.
Page 260 ...the world's most energy friendly microcontrollers Since the incoming signal is only sampled on positive clock edges, the width of the incoming pulses must be at least two 32.768 kHz clock periods wide for reliable detection by the LEUART receiver. They must also be shorter than half a UART baud period.
Page 261: Register Map
...the world's most energy friendly microcontrollers 18.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 LEUARTn_CTRL Control Register 0x004 LEUARTn_CMD Command Register 0x008 LEUARTn_STATUS Status Register 0x00C LEUARTn_CLKDIV Clock Control Register 0x010 LEUARTn_STARTFRAME Start Frame Register...
Page 262 ...the world's most energy friendly microcontrollers Name Reset Access Description TXDMAWU TX DMA Wakeup Set to wake the DMA controller up when in EM2 and space is available in the transmit buffer. Value Description While in EM2, the DMA controller will not get requests about space being available in the transmit buffer DMA is available in EM2 for the request about space available in the transmit buffer RXDMAWU RX DMA Wakeup...
Page 263 ...the world's most energy friendly microcontrollers Name Reset Access Description PARITY Parity-Bit Mode Determines whether parity bits are enabled, and whether even or odd parity should be used. Value Mode Description NONE Parity bits are not used EVEN Even parity are used. Parity bits are automatically generated and checked by hardware. Odd parity is used.
Page 264 ...the world's most energy friendly microcontrollers Name Reset Access Description Set to activate data reception on LEUn_RX. 18.5.3 LEUARTn_STATUS - Status Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) RXDATAV RX Data Valid Set when data is available in the receive buffer.
Page 265 ...the world's most energy friendly microcontrollers 18.5.5 LEUARTn_STARTFRAME - Start Frame Register (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p. 20) . Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 266 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) FERR Receive Data Framing Error Set if data in buffer has a framing error. Can be the result of a break condition. PERR Receive Data Parity Error Set if data in buffer has a parity error.
Page 267 ...the world's most energy friendly microcontrollers Name Reset Access Description 13:9 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) RXDATAP 0x000 RX Data Peek Use this register to access data read from the LEUART. 18.5.10 LEUARTn_TXDATAX - Transmit Buffer Data Extended Register (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p.
Page 268 ...the world's most energy friendly microcontrollers Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) TXDATA 0x00 TX Data This frame will be added to the transmit buffer.
Page 269 ...the world's most energy friendly microcontrollers Name Reset Access Description TX Complete Interrupt Flag Set after a transmission when both the TX buffer and shift register are empty. 18.5.13 LEUARTn_IFS - Interrupt Flag Set Register Offset Bit Position 0x030 Reset Access Name Name...
Page 270 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) SIGF Clear Signal-Frame Interrupt Flag Write to 1 to clear the SIGF interrupt flag. STARTF Clear Start-Frame Interrupt Flag Write to 1 to clear the STARTF interrupt flag.
Page 271 ...the world's most energy friendly microcontrollers Name Reset Access Description RXUF RX Underflow Interrupt Enable Enable interrupt on RX underflow. RXOF RX Overflow Interrupt Enable Enable interrupt on RX overflow. RXDATAV RX Data Valid Interrupt Enable Enable interrupt on RX data. TXBL TX Buffer Level Interrupt Enable Enable interrupt on TX buffer level.
Page 272 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) REGFREEZE Register Update Freeze When set, the update of the LEUART is postponed until this bit is cleared. Use this bit to update several registers simultaneously. Value Mode Description...
Page 273 ...the world's most energy friendly microcontrollers 18.5.19 LEUARTn_ROUTE - I/O Routing Register Offset Bit Position 0x054 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) LOCATION I/O Location Decides the location of the LEUART I/O pins.
Page 274: Timer - Timer/Counter
...the world's most energy friendly microcontrollers 19 TIMER - Timer/Counter Quick Facts What? 0 1 2 3 The TIMER (Timer/Counter) keeps track of timing and counts events, generates output waveforms and triggers timed actions in other peripherals. Why? USART Most applications have activities that need to be timed accurately with as little CPU intervention and energy consumption as TIMER...
Page 275: Functional Description
...the world's most energy friendly microcontrollers • Pulse width measurement • Two capture registers for each capture channel • Capture on either positive or negative edge • Capture on both edges • Optional digital noise filtering on capture inputs • Output Compare •...
Page 276 ...the world's most energy friendly microcontrollers Figure 19.1. TIMER Block Overview HFPERCLK Prescaler CNTCLK TIMERn Note: For sim plicity, all Counter TIMERn_CCx registers are control Update grouped together in the figure, condition but they all have individual Input Capture Registers TIMERn_CNT TIMERn_TOP Quadrature...
Page 277 ...the world's most energy friendly microcontrollers The RUNNING bit in TIMERn_STATUS indicates if the Timer is running or not. If the SYNC bit in TIMERn_CTRL is set, the Timer is started/stopped/reloaded (external pin or PRS) when any of the other timers are started/stopped/reloaded.
Page 278 ...the world's most energy friendly microcontrollers must not have a higher frequency than f /3 when running from a pin input or a PRS input with HFPERCLK FILT enabled in TIMERn_CCx_CTRL. When running from PRS without FILT, the frequency can be as high as f .
Page 279: Timer Quadrature Encoded Inputs
...the world's most energy friendly microcontrollers Figure 19.6. TIMER Quadrature Encoded Inputs Channel A ° Channel B Forward rotation (Channel A leads Channel B) Channel A Channel B ° Backward rotation (Channel B leads Channel A) In the Timer these inputs are tapped from the Compare/Capture channel 0 (Channel A) and 1 (Channel B) inputs before edge detection.
Page 280: Timer Counter Response In X2 Decoding Mode
...the world's most energy friendly microcontrollers Table 19.1. TIMER Counter Response in X2 Decoding Mode Channel A Channel B Rising Falling Increment Decrement Decrement Increment Figure 19.8. TIMER X2 Decoding Mode Channel A Channel B 19.3.1.6.2 X4 Decoding Mode In X4 Decoding mode, the counter increments or decrements on every edge of Channel A and Channel B, see Figure 19.9 (p.
Page 281 ...the world's most energy friendly microcontrollers 1. Input Capture 2. Output Compare 3. PWM 19.3.2.1 Input Pin Logic Each Compare/Capture channel can be configured as an input source for the Capture Unit or as external clock source for the Timer (see Figure 19.10 (p. 281) ). Compare/Capture channels 0 and 1 are the inputs for the Quadrature Decoder Mode.
Page 282: Timer Input Capture Buffer Functionality
...the world's most energy friendly microcontrollers Figure 19.11. TIMER Input Capture Buffer Functionality CCVB FIFO 19.3.2.2.2 Compare and PWM Mode When running in Output Compare or PWM mode, the value in TIMERn_CCx_CCV will be compared against the count value. In Compare mode the output can be configured to toggle, clear or set on compare match, overflow and underflow through the CMOA, COFOA and CUFOA fields in TIMERn_CCx_CTRL.
Page 283: Timer Input Capture
...the world's most energy friendly microcontrollers Figure 19.13. TIMER Input Capture Input TIMERn_CNT TIMERn_CCx _CCV prev. val prev. val TIMERn_CCx _CCVB Read TIMERn_CCx _CCVB 19.3.2.3.1 Period/Pulse-Width Capture Period and/or pulse-width capture can be achieved by setting the RISEA field in TIMERn_CTRL to Clear&Start, and select the wanted input from either external pin or PRS, see Figure 19.14 (p.
Page 284 ...the world's most energy friendly microcontrollers Figure 19.15. TIMER Block Diagram Showing Comparison Functionality Update Condition CNTCLK TIMERn_CNT TIMERn_TOP Overflow Underflow Note: For sim plicity, all TIMERn_CCx registers are grouped together in the figure, Com pare Match x but they all have individual Com pare Register and logic Com pare and TnCCR1[15:0...
Page 285: Timer Up-Count Frequency Generation
...the world's most energy friendly microcontrollers Figure 19.17. TIMER Up-count Frequency Generation TIMERn_TOP TIMERn_CCx _CCV The output frequency is given by Equation 19.2 (p. 285) TIMER Up-count Frequency Generation Equation / ( 2^(PRESC + 1) x (TOP + 1) x 2) (19.2) HFPERCLK 19.3.2.5 Pulse-Width Modulation (PWM)
Page 286: Timer Up/Down-Count Pwm Generation
...the world's most energy friendly microcontrollers = CCVx/TOP (19.5) 19.3.2.7 Up/Down-count (Dual-slope) PWM If the counter is set to up-down count and the Compare/Capture channel is put in PWM mode, dual slope PWM output will be generated by Figure 19.19 (p. 286) .The resolution (in bits) is given by Equation 19.6 (p.
Page 287 ...the world's most energy friendly microcontrollers When used for motor control, the PWM outputs TIM0_CC0, TIM0_CC1 and TIM0_CC2 are often connected to the high-side transistors of a triple half-bridge setup (UH, VH and WH), and the complementary outputs connected to the respective low-side transistors (UL, VL, WL shown in Figure 19.21 (p.
Page 288 ...the world's most energy friendly microcontrollers Figure 19.23. TIMER Polarity of Both Signals are Set as Active-High Original PWM TIM0_CC0 TIM0_CDTI0 Dead-time is specified individually for the rising and falling edge of the original PWM. These values are shared across all the three PWM channels of the DTI unit. A single prescaler value is provided for the DTI unit, meaning that both the rising and falling edge dead-times share prescaler value.
Page 289 ...the world's most energy friendly microcontrollers Figure 19.24. TIMER Output Polarities Original PWM TIM0_CC0 DTIPOL = 0 DTCINV = 0 TIM0_CDTI0 TIM0_CC0 DTIPOL = 1 DTCINV = 0 TIM0_CDTI0 TIM0_CC0 DTIPOL = 0 DTCINV = 1 TIM0_CDTI0 TIM0_CC0 DTIPOL = 1 DTCINV = 1 TIM0_CDTI0 Output generation on the individual DTI outputs can be disabled by configuring TIMER0_DTOGEN.
Page 290 ...the world's most energy friendly microcontrollers One or two PRS channels can be used as an error source. When PRS source 0 is selected as an error source, DTPRS0FSEL determines which PRS channel is used for this source. DTPRS1FSEL determines which PRS channel is selected as PRS source 1.
Page 291: Timer Events
...the world's most energy friendly microcontrollers If the interrupt flags are set and the corresponding interrupt enable bits in TIMERn_IEN) are set high, the Timer will send out an interrupt request. Each of the events will also lead to a one HFPERCLK TIMERn cycle high pulse on individual PRS outputs.
Page 292: Register Map
...the world's most energy friendly microcontrollers 19.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 TIMERn_CTRL Control Register 0x004 TIMERn_CMD Command Register 0x008 TIMERn_STATUS Status Register 0x00C TIMERn_IEN Interrupt Enable Register 0x010 TIMERn_IF Interrupt Flag Register...
Page 293: Register Description
...the world's most energy friendly microcontrollers 19.5 Register Description 19.5.1 TIMERn_CTRL - Control Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 27:24 PRESC Prescaler Setting...
Page 294 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description RELOADSTART Reload and start counter DMACLRACT DMA Request Clear on Active When this bit is set, the DMA requests are cleared when the corresponding DMA channel is active. This enables the timer DMA requests to be cleared without accessing the timer.
Page 295 ...the world's most energy friendly microcontrollers Name Reset Access Description Write a 1 to this bit to start timer 19.5.3 TIMERn_STATUS - Status Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:27 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CCPOL2 CC2 Polarity In Input Capture mode, this bit indicates the polarity of the edge that triggered capture in TIMERn_CC2_CCV.
Page 296 ...the world's most energy friendly microcontrollers Name Reset Access Description This bit indicates that TIMERn_CC0_CCV contains a valid capture value. These bits are only used in input capture mode and are cleared when CCMODE is written to 0b00 (Off). Value Description TIMERn_CC0_CCV does not contain a valid capture value(FIFO empty) TIMERn_CC0_CCV contains a valid capture value(FIFO not empty)
Page 297 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) ICBOF2 CC Channel 2 Input Capture Buffer Overflow Interrupt Enable Enable/disable Compare/Capture ch 2 input capture buffer overflow interrupt.
Page 298 ...the world's most energy friendly microcontrollers Name Reset Access Description This bit indicates that there has been an interrupt event on Compare/Capture channel 1. CC Channel 0 Interrupt Flag This bit indicates that there has been an interrupt event on Compare/Capture channel 0. Reserved To ensure compatibility with future devices, always write bits to 0.
Page 299 ...the world's most energy friendly microcontrollers 19.5.7 TIMERn_IFC - Interrupt Flag Clear Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) ICBOF2 CC Channel 2 Input Capture Buffer Overflow Interrupt Flag Clear Writing a 1 to this bit will clear Compare/Capture channel 2 input capture buffer overflow interrupt flag.
Page 300 ...the world's most energy friendly microcontrollers Name Reset Access Description These bits hold the TOP value for the counter. 19.5.9 TIMERn_TOPB - Counter Top Value Buffer Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 301 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:18 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 17:16 LOCATION I/O Location Decides the location of the CC pins. Value Mode Description...
Page 302 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description RISING Rising edges detected FALLING Falling edges detected BOTH Both edges detected NONE No edge detection, signal is left as it is 23:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) FILT Digital Filter Enable digital filter.
Page 303 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description Set output on compare match Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) COIST Compare Output Initial State This bit is only used in Output Compare and PWM mode.
Page 304 ...the world's most energy friendly microcontrollers 19.5.14 TIMERn_CCx_CCVP - CC Channel Value Peek Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 CCVP 0x0000...
Page 305 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:25 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) DTPRSEN DTI PRS Source Enable Enable/disable PRS as DTI input. 23:7 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 306 ...the world's most energy friendly microcontrollers Name Reset Access Description Set time span for the rising edge. Value Description DTRISET Rise time of DTRISET+1 prescaled HFPERCLK cycles Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) DTPRESC DTI Prescaler Setting Select prescaler for DTI.
Page 307 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description TRISTATE Tristate outputs 15:11 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 10:8 DTPRS1FSEL DTI PRS Fault Source 1 Select Select PRS channel for fault source 1.
Page 308 ...the world's most energy friendly microcontrollers Name Reset Access Description DTOGCC1EN DTI CC1 Output Generation Enable This bit enables/disables output generation for the CC1 output from the DTI. DTOGCC0EN DTI CC0 Output Generation Enable This bit enables/disables output generation for the CC0 output from the DTI. 19.5.20 TIMERn_DTFAULT - DTI Fault Register Offset Bit Position...
Page 309 ...the world's most energy friendly microcontrollers Name Reset Access Description DTPRS1FC DTI PRS1 Fault Clear Write 1 to this bit to clear PRS 1 fault. DTPRS0FC DTI PRS0 Fault Clear Write 1 to this bit to clear PRS 0 fault. 19.5.22 TIMERn_DTLOCK - DTI Configuration Lock Register Offset Bit Position...
Page 310: Rtc - Real Time Counter
...the world's most energy friendly microcontrollers 20 RTC - Real Time Counter Quick Facts What? The Real Time Counter (RTC) ensures timekeeping in low energy modes. Combined with two low power oscillators (XTAL or RC), 0 1 2 3 the RTC can run in EM2 with total current consumption less than 0.9 µA.
Page 311: Rtc Overview
...the world's most energy friendly microcontrollers Figure 20.1. RTC Overview Peripheral bus LFACLK Com pare 0 Com pare 1 RTC Control and Counter (CNT) (COMP0) (COMP1) Status Clear Com pare m atch 0 Com pare m atch 1 20.3.1 Counter The RTC is enabled by setting the EN bit in the RTC_CTRL register.
Page 312: Rtc Resolution Vs Overflow
...the world's most energy friendly microcontrollers Table 20.1. RTC Resolution Vs Overflow RTC_PRESC Resolution Overflow 30,5 µs 512 s 61,0 µs 1024 s 122 µs 2048 s 244 µs 1,14 hours 488 µs 2,28 hours 977 µs 4,55 hours 1,95 ms 9,10 hours 3,91 ms 18,2 hours...
Page 313 ...the world's most energy friendly microcontrollers 20.3.4 Debugrun By default, the RTC is halted when code execution is halted from the debugger. By setting the DEBUGRUN bit in the RTC_CTRL register, the RTC will continue to run even when the debugger is halted.
Page 314: Register Map
...the world's most energy friendly microcontrollers 20.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 RTC_CTRL Control Register 0x004 RTC_CNT Counter Value Register 0x008 RTC_COMP0 Compare Value Register 0 0x00C RTC_COMP1 Compare Value Register 1 0x010...
Page 315 ...the world's most energy friendly microcontrollers 20.5.2 RTC_CNT - Counter Value Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 23:0 0x000000 Counter Value...
Page 316 ...the world's most energy friendly microcontrollers Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 23:0 COMP1 0x000000 Compare Value 1 A compare match event occurs when CNT is equal to this value.
Page 317 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) COMP1 Set Compare match 1 Interrupt Flag Write to 1 to set the COMP1 interrupt flag. COMP0 Set Compare match 0 Interrupt Flag Write to 1 to set the COMP0 interrupt flag.
Page 318 ...the world's most energy friendly microcontrollers Name Reset Access Description Enable interrupt on overflow. 20.5.9 RTC_FREEZE - Freeze Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) REGFREEZE Register Update Freeze When set, the update of the RTC is postponed until this bit is cleared.
Page 319: Letimer - Low Energy Timer
...the world's most energy friendly microcontrollers 21 LETIMER - Low Energy Timer Quick Facts What? The LETIMER is a down-counter that can keep track of time and output configurable waveforms. Running on a 32.768 Hz clock 0 1 2 3 the LETIMER is available in EM2 with sub µA current consumption.
Page 320: Functional Description
...the world's most energy friendly microcontrollers • Repeat done • Optionally runs during debug 21.3 Functional Description An overview of the LETIMER module is shown in Figure 21.1 (p. 320) . The LETIMER is a 16-bit down-counter with two compare registers, LETIMERn_COMP0 and LETIMERn_COMP1. The LETIMERn_COMP0 register can optionally act as a top value for the counter.
Page 321: Letimer Repeat Modes
...the world's most energy friendly microcontrollers LETIMERn_CNT becomes equal to their value. When LETIMERn_CNT becomes equal to the value of LETIMERn_COMP0, the interrupt flag COMP0 in LETIMERn_IF is set, and when LETIMERn_CNT becomes equal to the value of LETIMERn_COMP1, the interrupt flag COMP1 in LETIMERn_IF is set. 21.3.3 Top Value If COMP0TOP in LETIMERn_CTRL is set, the value of LETIMERn_COMP0 acts as the top value of the timer, and LETIMERn_COMP0 is loaded into LETIMERn_CNT on timer underflow.
Page 322 ...the world's most energy friendly microcontrollers Figure 21.2. LETIMER State Machine for Free-running Mode Wait for positive clock edge If (STOP) RUNNING = 0 Else if (START) (RUNNING or START) RUNNING = 1 and !STOP End if START = 0 STOP = 0 CNT = = 0 CNT = CNT - 1...
Page 323 ...the world's most energy friendly microcontrollers Figure 21.3. LETIMER One-shot Repeat State Machine Wait for positive clock edge If (STOP) RUNNING = 0 RUNNING Else if (START) RUNNING = 1 End if START START = 0 STOP = 0 CNT = CNT - 1 CNT = = 0 CNT = = 0 CNT = CNT - 1...
Page 324 ...the world's most energy friendly microcontrollers Figure 21.4. LETIMER Buffered Repeat State Machine Wait for positive clock edge If (STOP) RUNNING = 0 Else if (START) RUNNING = 1 RUNNING End if START = 0 START STOP = 0 CNT = CNT - 1 CNT = = 0 CNT = = 0 CNT = CNT - 1...
Page 325: Letimer Clock Frequency
...the world's most energy friendly microcontrollers Figure 21.5. LETIMER Double Repeat State Machine Wait for positive clock edge If (STOP) RUNNING = 0 Else if (START) RUNNING = 1 RUNNING End if START = 0 START STOP = 0 CNT = CNT - 1 CNT = = 0 CNT = = 0 CNT = CNT - 1...
Page 326: Letimer Underflow Output Actions
...the world's most energy friendly microcontrollers continue running if triggered while it is running, so the multiple-triggering will only have an effect if you try to disable the RTC when it is being triggered. 21.3.3.5 Debug If DEBUGRUN in LETIMERn_CTRL is cleared, the LETIMER automatically stops counting when the CPU is halted during a debug session, and resumes operation when the CPU continues.
Page 327 ...the world's most energy friendly microcontrollers Some simple waveforms generated with the different output modes are shown in Figure 21.6 (p. 327) . For the example, REPMODE in LETIMERn_CTRL has been cleared, COMP0TOP also in LETIMERn_CTRL has been set and LETIMERn_COMP0 has been written to 3. As seen in the figure, LETIMERn_COMP0 now decides the length of the signal periods.
Page 328: Letimer Triggered Operation
...the world's most energy friendly microcontrollers Figure 21.8. LETIMER Dual Output UFOA0 = 10 UFOA1 = 10 REP0 = 2 REP0 = 2 REP1 = 7 REP0 = 3 REP1 = 3 START START START LETn_O0 LETn_O1 21.3.5 Examples This section presents a couple of usage examples for the LETIMER. 21.3.5.1 Triggered Output Generation Example 21.1.
Page 329: Letimer Continuous Operation
...the world's most energy friendly microcontrollers 21.3.5.2 Continuous Output Generation Example 21.2. LETIMER Continuous Output Generation In some scenarios, it might be desired to make LETIMER generate a continuous waveform. Very simple constant waveforms can be generated without the repeat counter as shown in Figure 21.6 (p. 327) , but to generate changing waveforms, using the repeat counter and buffer registers can prove advantageous.
Page 330 ...the world's most energy friendly microcontrollers Multiple LETIMER cycles are required to write a value to the LETIMER registers. The example in Figure 21.10 (p. 329) assumes that writes are done in advance so they arrive in the LETIMER as described in the figure. Figure 21.11 (p.
Page 331 ...the world's most energy friendly microcontrollers 21.3.6 Register access Since this module is a Low Energy Peripheral, and runs off a clock which is asynchronous to the HFCORECLK, special considerations must be taken when accessing registers. Please refer to Section 5.3.1.1 (p. 21) for a description on how to perform register accesses to Low Energy Peripherals. www.silabs.com 2014-07-02 - Gecko Family - d0001_Rev1.30...
Page 332: Register Map
...the world's most energy friendly microcontrollers 21.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 LETIMERn_CTRL Control Register 0x004 LETIMERn_CMD Command Register 0x008 LETIMERn_STATUS Status Register 0x00C LETIMERn_CNT Counter Value Register 0x010 LETIMERn_COMP0 Compare Value Register 0...
Page 333 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Description A compare match on RTC compare channel 1 starts the LETIMER if the LETIMER is not already started RTCC0TEN RTC Compare 0 Trigger Enable Allows the LETIMER to be started on a compare match on RTC compare channel 0. Value Description LETIMER is not affected by RTC compare channel 0...
Page 334 ...the world's most energy friendly microcontrollers 21.5.2 LETIMERn_CMD - Command Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CTO1 Clear Toggle Output 1 Set to drive toggle output 1 to its idle value...
Page 335 ...the world's most energy friendly microcontrollers 21.5.4 LETIMERn_CNT - Counter Value Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 0x0000 Counter Value...
Page 336 ...the world's most energy friendly microcontrollers Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 COMP1 0x0000 Compare Value 1 Compare and optionally buffered top value for LETIMER 21.5.7 LETIMERn_REP0 - Repeat Counter Register 0 (Async Reg)
Page 337 ...the world's most energy friendly microcontrollers Name Reset Access Description REP1 0x00 Repeat Counter 1 Optional repeat counter or buffer for REP0 21.5.9 LETIMERn_IF - Interrupt Flag Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 338 ...the world's most energy friendly microcontrollers Name Reset Access Description COMP1 Set Compare Match 1 Interrupt Flag Write to 1 to set the COMP1 interrupt flag. COMP0 Set Compare Match 0 Interrupt Flag Write to 1 to set the COMP0 interrupt flag. 21.5.11 LETIMERn_IFC - Interrupt Flag Clear Register Offset Bit Position...
Page 339 ...the world's most energy friendly microcontrollers Name Reset Access Description Underflow Interrupt Enable Set to enable interrupt on the UF interrupt flag. COMP1 Compare Match 1 Interrupt Enable Set to enable interrupt on the COMP1 interrupt flag. COMP0 Compare Match 0 Interrupt Enable Set to enable interrupt on the COMP0 interrupt flag.
Page 340 ...the world's most energy friendly microcontrollers Name Reset Access Description Set when the value written to COMP0 is being synchronized. CMD Register Busy Set when the value written to CMD is being synchronized. CTRL CTRL Register Busy Set when the value written to CTRL is being synchronized. 21.5.15 LETIMERn_ROUTE - I/O Routing Register Offset Bit Position...
Page 341: Pcnt - Pulse Counter
...the world's most energy friendly microcontrollers 22 PCNT - Pulse Counter Quick Facts What? 0 1 2 3 The Pulse Counter (PCNT) decodes incoming pulses. The module has a quadrature mode which may be used to decode the speed and direction of a mechanical shaft.
Page 342: Pcnt Overview
...the world's most energy friendly microcontrollers Figure 22.1. PCNT Overview CMU (conceptual) LFACLK Clock switch Peripheral bus OVR_SINGLE Edge Pulse Width Inverter detector Filter TOPB EXTCLK_SINGLE EXTCLK_QUAD Quadrature Inverter decoder 22.3.1 Pulse Counter Modes The pulse counter can operate in single input oversampling mode (OVSSINGLE), externally clocked single input counter mode (EXTCLKSINGLE) and externally clocked quadrature decoder mode (EXTCLKQUAD).
Page 343 ...the world's most energy friendly microcontrollers unintended pulses from devices such as mechanical switches, and is therefore most suited to take input from electronic sensors etc. that generate single wire pulses. Only the underflow (UF) and overflow (OF) interrupt flags are set in this mode. 22.3.1.3 Externally Clocked Quadrature Decoder Mode This mode is enabled by writing EXTCLKQUAD to the MODE field in PCNTn_CTRL and disabled by writing DISABLE to the same field.
Page 344: Pcnt Quad Mode Counter Control Function
...the world's most energy friendly microcontrollers The direction of the quadrature code and control of the counter is generated by the simple binary function outlined by Table 22.1 (p. 344) . Note that this function also filters some invalid inputs that may occur when the shaft changes direction or temporarily toggles direction.
Page 345 ...the world's most energy friendly microcontrollers 22.3.4 Input Filter An optional pulse width filter is available in OVSSINGLE mode. The filter is enabled by writing 1 to the FILT bit in the PCNTn_CTRL register. When enabled, the high and low periods of PCNTn_S0IN must be stable for 5 consecutive clock cycles before the edge is passed to the edge detector.
Page 346 ...the world's most energy friendly microcontrollers Figure 22.3. PCNT Direction Change Interrupt (DIRCNG) Generation Standard async handshake interface Invalid pulse generated when the shaft changes direction PCNTn_S0IN PCNTn_S1IN Interrupt n+ 1 n+ 2 n+ 3 n+ 2 PCNTn_CNT Delay from the shaft physically changed direction until the counter direction is changed and the interrupt is generated...
Page 347: Register Map
...the world's most energy friendly microcontrollers 22.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 PCNTn_CTRL Control Register 0x004 PCNTn_CMD Command Register 0x008 PCNTn_STATUS Status Register 0x00C PCNTn_CNT Counter Value Register 0x010 PCNTn_TOP Top Value Register...
Page 348 Load TOPB Immediately This bit has no effect since TOPB is not buffered and it is loaded directly into TOP. For EFM32G revisions A and B: Load PCNTn_TOPB into PCNTn_TOP. Please see the device datasheet for a description on how to extract the chip revision.
Page 349 ...the world's most energy friendly microcontrollers Name Reset Access Description Current Counter Direction Current direction status of the counter. This bit is valid in EXTCLKQUAD mode only. Value Mode Description Up counter mode (clockwise in EXTCLKQUAD mode with the NEDGE bit in PCNTn_CTRL set to 0).
Page 350 Counter Top Buffer Loaded automatically to TOP when written. For EFM32G revisions A and B: Loaded into TOP when LTOPBIM in PCNTn_CMD register is set. Please see the device datasheet for a description on how to extract the chip revision.
Page 351 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) DIRCNG Direction Change Detect Interrupt Set Write to 1 to set the direction change interrupt flag Overflow Interrupt Set Write to 1 to set the overflow interrupt flag Underflow interrupt set...
Page 352 ...the world's most energy friendly microcontrollers Name Reset Access Description Enable the overflow interrupt Underflow Interrupt Enable Enable the underflow interrupt 22.5.11 PCNTn_ROUTE - I/O Routing Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 353 ...the world's most energy friendly microcontrollers 22.5.13 PCNTn_SYNCBUSY - Synchronization Busy Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) TOPB TOPB Register Busy Set when the value written to TOPB is being synchronized.
Page 354: Acmp - Analog Comparator
...the world's most energy friendly microcontrollers 23 ACMP - Analog Comparator Quick Facts What? The ACMP (Analog Comparator) compares two analog signals and returns a digital value telling which is greater. 0 1 2 3 Why? Applications often do not need to know the exact value of an analog signal, only if it has passed a certain threshold.
Page 355: Functional Description
...the world's most energy friendly microcontrollers • Comparator output direct on PRS • Comparator output on GPIO through alternate functionality • Output inversion available 23.3 Functional Description An overview of the ACMP is shown in Figure 23.1 (p. 355) . Figure 23.1.
Page 356: Bias Configuration
...the world's most energy friendly microcontrollers 23.3.2 Response Time There is a delay from when the actual input voltage changes polarity, to when the output toggles. This period is called the response time and can be altered by increasing or decreasing the bias current to the comparator through the BIASPROG, FULLBIASPROG and HALFBIAS fields in the ACMPn_CTRL register, as illustrated in Table 23.1 (p.
Page 357: Vdd Scaled
...the world's most energy friendly microcontrollers Figure 23.2. 20 mV Hysteresis Selected + 20m V Tim e - 20m V ACMPOUT without hysteresis ACMPOUT with hysteresis 23.3.4 Input Selection The POSSEL and NEGSEL fields in ACMPn_INPUTSEL controls which signals are connected to the two inputs of the comparator.
Page 358: Capacitive Sensing Set-Up
...the world's most energy friendly microcontrollers Figure 23.3. Capacitive Sensing Set-up Buttons POSSEL DD_SCALED 23.3.6 Interrupts and PRS Output The analog comparator includes an edge triggered interrupt flag (EDGE in ACMPn_IF). If either IRISE and/or IFALL in ACMPn_CTRL is set, the EDGE interrupt flag will be set on rising and/or falling edge of the comparator output, respectively.
Page 359: Register Map
...the world's most energy friendly microcontrollers 23.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 ACMPn_CTRL Control Register 0x004 ACMPn_INPUTSEL Input Selection Register 0x008 ACMPn_STATUS Status Register 0x00C ACMPn_IEN Interrupt Enable Register 0x010 ACMPn_IF Interrupt Flag Register...
Page 360 ...the world's most energy friendly microcontrollers Name Reset Access Description 10:8 WARMTIME Warm-up Time Set analog comparator warm-up time. Value Mode Description 4CYCLES 4 HFPERCLK cycles. 8CYCLES 8 HFPERCLK cycles. 16CYCLES 16 HFPERCLK cycles. 32CYCLES 32 HFPERCLK cycles. 64CYCLES 64 HFPERCLK cycles. 128CYCLES 128 HFPERCLK cycles.
Page 361 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 29:28 CSRESSEL Capacitive Sense Mode Internal Resistor Select These bits select the resistance value for the internal capacitive sense resistor. Resulting actual resistor values are given in the device datasheets.
Page 362 ...the world's most energy friendly microcontrollers 23.5.3 ACMPn_STATUS - Status Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) ACMPOUT Analog Comparator Output Analog comparator output value.
Page 363 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) WARMUP Warm-up Interrupt Flag Indicates that the analog comparator warm-up period is finished. EDGE Edge Triggered Interrupt Flag Indicates that there has been a rising or falling edge on the analog comparator output.
Page 364 ...the world's most energy friendly microcontrollers 23.5.8 ACMPn_ROUTE - I/O Routing Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) LOCATION I/O Location Decides the location of the ACMP I/O pin.
Page 365: Vcmp - Voltage Comparator
...the world's most energy friendly microcontrollers 24 VCMP - Voltage Comparator Quick Facts What? 0 1 2 3 The Voltage Supply Comparator (VCMP) monitors the input voltage supply and generates software interrupts on events using as little as 100 nA. Why? The VCMP can be used for simple power supply monitoring, e.g.
Page 366: Functional Description
...the world's most energy friendly microcontrollers 24.3 Functional Description An overview of the VCMP is shown in Figure 24.1 (p. 366) . Figure 24.1. VCMP Overview Warm up interrupt Warm - up TRIGLEVEL VCMPACT counter Edge interrupt Scaler VCMPOUT INACTVAL BIASPROG HALFBIAS LPREF...
Page 367: Dd Trigger Level
...the world's most energy friendly microcontrollers BIAS Bias Current (µA) HALFBIAS=0 HALFBIAS=1 0b0100 0b0101 0b0110 0b0111 0b1000 0b1001 0b1010 0b1011 0b1100 0b1101 0b1110 0b1111 24.3.3 Hysteresis In the voltage supply comparator, hysteresis can be enabled by setting HYSTEN in VCMP_CTRL. When HYSTEN is set, the digital output will not toggle until the positive input voltage is at least 20mV above or below the negative input voltage.
Page 368 ...the world's most energy friendly microcontrollers 24.3.5 Interrupts and PRS Output The VCMP includes an edge triggered interrupt flag (EDGE in VCMP_IF). If either IRISE and/or IFALL in VCMPn_CTRL is set, the EDGE interrupt flag will be set on rising and/or falling edge of the comparator output respectively.
Page 369: Register Map
...the world's most energy friendly microcontrollers 24.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 VCMP_CTRL Control Register 0x004 VCMP_INPUTSEL Input Selection Register 0x008 VCMP_STATUS Status Register 0x00C VCMP_IEN Interrupt Enable Register 0x010 VCMP_IF Interrupt Flag Register...
Page 370 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description 512CYCLES 512 HFPERCLK cycles Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) HYSTEN Hysteresis Enable Enable hysteresis. Value Description No hysteresis...
Page 371 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) VCMPOUT Voltage Supply Comparator Output Voltage supply comparator output value VCMPACT Voltage Supply Comparator Active Voltage supply comparator active status.
Page 372 ...the world's most energy friendly microcontrollers 24.5.6 VCMP_IFS - Interrupt Flag Set Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) WARMUP Warm-up Interrupt Flag Set Write to 1 to set warm-up finished interrupt flag...
Page 373: Adc - Analog To Digital Converter
...the world's most energy friendly microcontrollers 25 ADC - Analog to Digital Converter Quick Facts What? The ADC is used to convert analog signals into a digital representation and features 8 external input channels 0 1 2 3 Why? In many applications there is a need to measure analog signals and record them in a digital representation, without exhausting your energy source.
Page 374: Functional Description
...the world's most energy friendly microcontrollers • Programmable scan sequence • Up to 8 configurable samples in scan sequence • Mask to select which pins are included in the sequence • Triggered by software or PRS input • One shot or repetitive mode •...
Page 375: Adc Overview
...the world's most energy friendly microcontrollers Figure 25.1. ADC Overview ADCn_CTRL ADCn_SINGLEDATA ADCn_CMD ADCn_SCANDATA ADCn_SINGLECTRL ADCn_STATUS ADCn_SCANCTRL Oversam pling filter Sequencer HFPERCLK ADC_CLK ADCn Prescaler Result buffer ADCn_CH0 ADCn_CH1 Control ADCn_CH2 ADCn_CH3 ADCn_CH4 ADCn_CH5 ADCn_CH6 ADCn_CH7 Tem p DAC0/ OPA0 DAC1/ OPA1 1.25 V 2.5 V...
Page 376: Adc Conversion Timing
...the world's most energy friendly microcontrollers Figure 25.2. ADC Conversion Timing HFPERCLK ADCn Prescaled clock (4x ) SINGLEAT/ ADC action Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCANAT...
Page 377 ...the world's most energy friendly microcontrollers Figure 25.3. ADC Analog Power Consumption With Different WARMUPMODE Settings Bandgap reference warm - up ADC warm - up ADC conversion ADC enabled Conversion trigger Conversion trigger Power NORMAL 5 µs Tim e 1 µs 1 µs Power KEEPSCANREFWARM 5 µs...
Page 378: Adc Temperature Measurement
...the world's most energy friendly microcontrollers Figure 25.4. ADC RC Input Filter Configuration Input 25.3.4.2 Temperature Measurement The ADC includes an internal temperature sensor. This sensor is characterized during production and the temperature readout from the ADC at production temperature, ADC0_TEMP_0_READ_1V25, is given in the Device Information (DI) page.
Page 379 ...the world's most energy friendly microcontrollers bitfields scale the current of ADC bandgap reference, and the COMPBIAS bits provide an additional bias programming for the ADC comparator as illustrated in Figure 25.5 (p. 379) . The electrical characteristics given in the datasheet require the bias configuration to be set to the default values, where no other bias values are given.
Page 380: Adc Conversion Tailgating
...the world's most energy friendly microcontrollers single sample just before a scan trigger can delay the start of the scan sequence, thus causing jitter in sample rate. To solve this, conversion tailgating can be chosen by setting TAILGATE in ADCn_CTRL. When this bit is set, any triggered single samples will wait for the next scan sequence to finish before activating (see Figure 25.6 (p.
Page 381: Adc Differential Conversion
...the world's most energy friendly microcontrollers Table 25.2. ADC Differential Conversion Results Input/Reference Binary Hex value 011111111111 0.25 001111111111 1/2048 000000000001 000000000000 -1/2048 111111111111 -0.25 101111111111 -0.5 100000000000 25.3.7.6 Resolution The ADC gives out 12-bit results, by default. However, if full 12-bit resolution is not needed, it is possible to speed up the conversion by selecting a lower resolution (N = 6 or 8 bits).
Page 382: Adc Results Representation
...the world's most energy friendly microcontrollers 25.3.7.8 Adjustment By default, all results are right adjusted, with the LSB of the result in bit position 0 (zero). In differential mode the signed bit is extended up to bit 31, but in single ended mode the bits above the result are read as 0.
Page 383: Calibration Register Effect
...the world's most energy friendly microcontrollers The effects of changing the calibration register values are given in Table 25.5 (p. 383) . Step by step calibration procedures for offset and gain are given in Section 25.3.10.1 (p. 383) and Section 25.3.10.2 (p. 383) . Table 25.5.
Page 384: Register Map
...the world's most energy friendly microcontrollers 25.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 ADCn_CTRL Control Register 0x004 ADCn_CMD Command Register 0x008 ADCn_STATUS Status Register 0x00C ADCn_SINGLECTRL Single Sample Control Register 0x010 ADCn_SCANCTRL Scan Control Register...
Page 385 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description X1024 1024 samples for each conversion result X2048 2048 samples for each conversion result X4096 4096 samples for each conversion result 23:21 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 20:16 TIMEBASE 0x1F...
Page 386 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) SCANSTOP Scan Sequence Stop Write a 1 to stop scan sequence. SCANSTART Scan Sequence Start Write a 1 to start scan sequence.
Page 387 ...the world's most energy friendly microcontrollers Name Reset Access Description Reference selected for scan mode is warmed up. SINGLEREFWARM Single Reference Warmed Up Reference selected for single mode is warmed up. Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) SCANACT Scan Conversion Active Scan sequence is active or has pending conversions.
Page 388 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description 128CYCLES 128 ADC_CLK cycles acquisition time for single sample 256CYCLES 256 ADC_CLK cycles acquisition time for single sample Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 18:16 Single Sample Reference Selection Select reference to ADC single sample mode.
Page 389 ...the world's most energy friendly microcontrollers Name Reset Access Description Single Sample Result Adjustment Select single sample result adjustment. Value Mode Description RIGHT Results are right adjusted LEFT Results are left adjusted DIFF Single Sample Differential Mode Select single ended or differential input. Value Description Single ended input...
Page 390 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description 1CYCLE 1 ADC_CLK cycle acquisition time for scan samples 2CYCLES 2 ADC_CLK cycles acquisition time for scan samples 4CYCLES 4 ADC_CLK cycles acquisition time for scan samples 8CYCLES 8 ADC_CLK cycles acquisition time for scan samples 16CYCLES...
Page 391 ...the world's most energy friendly microcontrollers Name Reset Access Description Scan Sequence Result Adjustment Select scan sequence result adjustment. Value Mode Description RIGHT Results are right adjusted LEFT Results are left adjusted DIFF Scan Sequence Differential Mode Select single ended or differential input. Value Description Single ended input...
Page 392 ...the world's most energy friendly microcontrollers 25.5.7 ADCn_IF - Interrupt Flag Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) SCANOF Scan Result Overflow Interrupt Flag Indicates scan result overflow when this bit is set.
Page 393 ...the world's most energy friendly microcontrollers 25.5.9 ADCn_IFC - Interrupt Flag Clear Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) SCANOF Scan Result Overflow Interrupt Flag Clear Write to 1 to clear scan result overflow interrupt flag.
Page 394 ...the world's most energy friendly microcontrollers 25.5.11 ADCn_SCANDATA - Scan Conversion Result Data Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:0 DATA 0x00000000 Scan Conversion Result Data The register holds the results from the last scan conversion. Reading this field clears the SCANDV bit in the ADCn_STATUS register. 25.5.12 ADCn_SINGLEDATAP - Single Conversion Result Data Peek Register Offset...
Page 395 ...the world's most energy friendly microcontrollers 25.5.13 ADCn_SCANDATAP - Scan Sequence Result Data Peek Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:0 DATAP 0x00000000 Scan Conversion Result Data Peek The register holds the results from the last scan conversion. Reading this field will not clear SCANDV in ADCn_STATUS or single DMA request.
Page 396 ...the world's most energy friendly microcontrollers Name Reset Access Description This register contains the offset calibration value used with single conversions. This field is set to the production offset calibration value for the 1V25 internal reference during reset, hence the reset value might differ from device to device. The field is encoded as a signed 2's complement number.
Page 397: Dac - Digital To Analog Converter
...the world's most energy friendly microcontrollers 26 DAC - Digital to Analog Converter Quick Facts What? The DAC is designed for low energy consumption, but can also provide very good performance. It can convert digital values 0 1 2 3 to analog signals at up to 500 kilo samples/ second and with 12-bit accuracy.
Page 398: Functional Description
...the world's most energy friendly microcontrollers • Output to ADC • Sine generation mode • Optional high strength line driver 26.3 Functional Description An overview of the DAC module is shown in Figure 26.1 (p. 398) . Figure 26.1. DAC Overview DACn_OUT0 Ch 0 CH0DATA...
Page 399: Dac Clock Prescaling
...the world's most energy friendly microcontrollers a combined data register, DACn_COMBDATA, where the data values for both channels can be written simultaneously. Writing to this register will start all enabled channels. If the PRSEN bit in DACn_CHxCTRL is set, a DAC conversion on channel x will not be started by data write, but when a positive one HFPERCLK cycle pulse is received on the PRS input selected by PRSSEL in DACn_CHxCTRL.
Page 400: Dac Single Ended Output Voltage
...the world's most energy friendly microcontrollers Figure 26.2. DAC Bias Programming Reference BIASPROG Current HALFBIAS Internal DAC output bandgap buffer reference The minimum value of the BIASPROG bit-field of the DACn_BIASPROG register (i.e. BIASPROG=0b0000) represents the minimum bias current. Similarly BIASPROG=0b1111 represents the maximum bias current.
Page 401: Dac Sine Mode
...the world's most energy friendly microcontrollers table. The sine signal is controlled by the PRS line selected by CH0PRSSEL in DACn_CH0CTRL. When the PRS line is low, a voltage of Vref/2 will be produced. When the line is high, a sine wave will be produced.
Page 402 ...the world's most energy friendly microcontrollers 26.3.9 Calibration The DAC contains a calibration register, DACn_CAL, where calibration values for both offset and gain correction can be written. Offset calibration is done separately for each channel through the CHxOFFSET bit-fields. Gain is calibrated in one common register field, GAIN. The gain calibration is linked to the reference and when the reference is changed, the gain must be re-calibrated.
Page 403: Register Map
...the world's most energy friendly microcontrollers 26.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 DACn_CTRL Control Register 0x004 DACn_STATUS Status Register 0x008 DACn_CH0CTRL Channel 0 Control Register 0x00C DACn_CH1CTRL Channel 1 Control Register 0x010 DACn_IEN...
Page 404 ...the world's most energy friendly microcontrollers Name Reset Access Description 15:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) REFSEL Reference Selection Select reference. Value Mode Description 1V25 Internal 1.25 V bandgap reference Internal 2.5 V bandgap reference VDD reference CH0PRESCRST...
Page 405 ...the world's most energy friendly microcontrollers 26.5.2 DACn_STATUS - Status Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CH1DV Channel 1 Data Valid This bit is set high when CH1DATA is written and is set low when CH1DATA is used in conversion.
Page 406 ...the world's most energy friendly microcontrollers Name Reset Access Description REFREN Channel 0 Automatic Refresh Enable Set to enable automatic refresh of channel 0. Refresh period is set by REFRSEL in DACn_CTRL. Value Description Channel 0 is not refreshed automatically Channel 0 is refreshed automatically Channel 0 Enable Enable/disable channel 0.
Page 407 ...the world's most energy friendly microcontrollers 26.5.5 DACn_IEN - Interrupt Enable Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CH1UF Channel 1 Conversion Data Underflow Interrupt Enable Enable/disable channel 1 data underflow interrupt.
Page 408 ...the world's most energy friendly microcontrollers 26.5.7 DACn_IFS - Interrupt Flag Set Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) CH1UF Channel 1 Data Underflow Interrupt Flag Set Write to 1 to set channel 1 Data Underflow interrupt flag.
Page 409 ...the world's most energy friendly microcontrollers 26.5.9 DACn_CH0DATA - Channel 0 Data Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 11:0 DATA 0x000...
Page 410 ...the world's most energy friendly microcontrollers Name Reset Access Description 27:16 CH1DATA 0x000 Channel 1 Data Data written to this register will be written to DATA in DACn_CH1DATA. 15:12 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 11:0 CH0DATA 0x000...
Page 411 ...the world's most energy friendly microcontrollers Name Reset Access Description Set this bit to halve the bias current. Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) BIASPROG Bias Programming Value These bits control the bias current level.
Page 412: Aes - Advanced Encryption Standard Accelerator
How? I am fine !T4/ #2 High AES throughput allows the EFM32G to spend more time in lower energy modes. In addition, specialized data access functions allow autonomous DMA/AES operation in both EM0 and EM1.
Page 413 ...the world's most energy friendly microcontrollers Figure 27.1. AES Key and Data Definitions Encryption PlainTex t CipherTex t Decryption Encryption PlainKey CipherKey Decryption 27.3.1 Encryption/Decryption The AES module can be set to encrypt or decrypt by clearing/setting the DECRYPT bit in AES_CTRL. The AES256 bit in AES_CTRL configures the size of the key used for encryption/decryption.
Page 414 ...the world's most energy friendly microcontrollers (n=A, B, C or D). Writing DATA3-DATA0 is then done through 4 consecutive writes to AES_DATA (or AES_XORDATA), starting with the word which is to be written to DATA0. For each write, the words will be word wise barrel shifted towards the least significant word.
Page 415 ...the world's most energy friendly microcontrollers • DATAWR: Cleared on a AES_DATA write or AES_CTRL write • XORDATAWR: Cleared on a AES_XORDATA write or AES_CTRL write • DATARD: Cleared on a AES_DATA read or AES_CTRL write • KEYWR: Cleared on a AES_KEYHn write or AES_CTRL write 27.3.5 Block Chaining Example Example 27.1 (p.
Page 416: Register Map
...the world's most energy friendly microcontrollers 27.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 AES_CTRL Control Register 0x004 AES_CMD Command Register 0x008 AES_STATUS Status Register 0x00C AES_IEN Interrupt Enable Register 0x010 AES_IF Interrupt Flag Register...
Page 417 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Description AES-128 mode AES-256 mode DECRYPT Decryption/Encryption Mode Select encryption or decryption. Value Description AES Encryption AES Decryption 27.5.2 AES_CMD - Command Register Offset Bit Position 0x004 Reset Access Name Name Reset...
Page 418 ...the world's most energy friendly microcontrollers 27.5.4 AES_IEN - Interrupt Enable Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) DONE Encryption/Decryption Done Interrupt Enable Enable/disable interrupt on encryption/decryption done.
Page 419 ...the world's most energy friendly microcontrollers 27.5.7 AES_IFC - Interrupt Flag Clear Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) DONE Encryption/Decryption Done Interrupt Flag Clear Write to 1 to clear encryption/decryption done interrupt flag...
Page 420 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:0 XORDATA 0x00000000 XOR Data Access Access data with XOR function through this register. 27.5.10 AES_KEYLA - KEY Low Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:0 KEYLA...
Page 421 ...the world's most energy friendly microcontrollers 27.5.12 AES_KEYLC - KEY Low Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:0 KEYLC 0x00000000 Key Low Access C Access the low key words through this register. 27.5.13 AES_KEYLD - KEY Low Register Offset Bit Position 0x03C...
Page 422 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:0 KEYHA 0x00000000 Key High Access A Access the high key words through this register. 27.5.15 AES_KEYHB - KEY High Register Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:0...
Page 423 ...the world's most energy friendly microcontrollers 27.5.17 AES_KEYHD - KEY High Register Offset Bit Position 0x04C Reset Access Name Name Reset Access Description 31:0 KEYHD 0x00000000 Key High Access D Access the high key words through this register. www.silabs.com 2014-07-02 - Gecko Family - d0001_Rev1.30...
Page 424: Gpio - General Purpose Input/Output
28.1 Introduction In the EFM32G devices the General Purpose Input/Output (GPIO) pins are organized into ports with up to 16 pins each. These pins can individually be configured as either an output or input. More advanced configurations like open-drain, filtering and drive strength can also be configured individually for the pins.
Page 425: Functional Description
...the world's most energy friendly microcontrollers • Glitch suppression input filter. • Analog connection to e.g. ADC or LCD. • Alternate functions (e.g. peripheral outputs and inputs) • Routed to several locations on the device • Pin connections can be enabled individually •...
Page 426: Pin Configuration
...the world's most energy friendly microcontrollers Figure 28.1. Pin Configuration Alternate function override Alternate function output enable Alternate function data out Port Control Output enable Output enable Data out Output value DOUT protection Pull- up enable Pull- down enable MODEn[3:0] Input enable ESD diode Filter enable...
Page 427: Open-Drain
...the world's most energy friendly microcontrollers MODEn Input Output DOUT Pull- Pull- Alt. Input Description down strength Filter Input enabled with pull-up 0b0011 Input enabled with pull-down and filter Input enabled with pull-up and filter 0b0100 Push-pull Push-pull 0b0101 Push-pull with alt. drive strength 0b0110 Open Open-source...
Page 428 ...the world's most energy friendly microcontrollers Figure 28.3. Push-Pull Configuration Output Enable DOUT Input Enable When MODEn is 0110 or 0111, the pin operates in open-source mode, the latter with a pull-down resistor. When driving a high value in open-source mode, the pull-down is disconnected to save power. For the remaining MODEn values, i.e.
Page 429 ...the world's most energy friendly microcontrollers function’s output data and output enable signals override the data output and output enable signals from the GPIO. However, the pin configuration stays as set in GPIO_Px_MODEL, GPIO_Px_MODEH and GPIO_Px_DOUT registers. I.e. the pin configuration must be set to output enable in GPIO for a peripheral to be able to use the pin as an output.
Page 430 ...the world's most energy friendly microcontrollers while the odd is triggered by odd flags. The interrupt flags can be set and cleared by software by writing the GPIO_IFS and GPIO_IFC registers, see Example 28.1 (p. 430) . Since the external interrupts are asynchronous, they are sensitive to noise.
Page 431: Register Map
...the world's most energy friendly microcontrollers 28.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 GPIO_PA_CTRL Port Control Register 0x004 GPIO_PA_MODEL Port Pin Mode Low Register 0x008 GPIO_PA_MODEH Port Pin Mode High Register 0x00C GPIO_PA_DOUT Port Data Out Register...
Page 432: Register Description
...the world's most energy friendly microcontrollers Offset Name Type Description 0x0A0 GPIO_PE_DOUTSET Port Data Out Set Register 0x0A4 GPIO_PE_DOUTCLR Port Data Out Clear Register 0x0A8 GPIO_PE_DOUTTGL Port Data Out Toggle Register 0x0AC GPIO_PE_DIN Port Data In Register 0x0B0 GPIO_PE_PINLOCKN Port Unlocked Pins Register 0x0B4 GPIO_PF_CTRL Port Control Register...
Page 433 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description LOWEST 0.1 mA drive current HIGH 20 mA drive current 1 mA drive current 28.5.2 GPIO_Px_MODEL - Port Pin Mode Low Register Offset Bit Position 0x004 Reset Access Name Name...
Page 434 ...the world's most energy friendly microcontrollers 28.5.3 GPIO_Px_MODEH - Port Pin Mode High Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:28 MODE15 Pin 15 Mode Configure mode for pin 15. Enumeration is equal to MODE8. 27:24 MODE14 Pin 14 Mode...
Page 435 ...the world's most energy friendly microcontrollers 28.5.4 GPIO_Px_DOUT - Port Data Out Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 DOUT 0x0000...
Page 436 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 DOUTCLR 0x0000 Data Out Clear Write bits to 1 to clear corresponding bits in GPIO_Px_DOUT. Bits written to 0 will have no effect. 28.5.7 GPIO_Px_DOUTTGL - Port Data Out Toggle Register Offset Bit Position...
Page 437 ...the world's most energy friendly microcontrollers 28.5.9 GPIO_Px_PINLOCKN - Port Unlocked Pins Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 PINLOCKN 0xFFFF...
Page 438 ...the world's most energy friendly microcontrollers Name Reset Access Description Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 22:20 EXTIPSEL5 External Interrupt 5 Port Select Select input port for external interrupt 5. Value Mode Description...
Page 439 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description PORTF Port F pin 1 selected for external interrupt 1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) EXTIPSEL0 External Interrupt 0 Port Select Select input port for external interrupt 0.
Page 440 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description PORTA Port A pin 13 selected for external interrupt 13 PORTB Port B pin 13 selected for external interrupt 13 PORTC Port C pin 13 selected for external interrupt 13 PORTD Port D pin 13 selected for external interrupt 13 PORTE...
Page 441 ...the world's most energy friendly microcontrollers Name Reset Access Description Select input port for external interrupt 8. Value Mode Description PORTA Port A pin 8 selected for external interrupt 8 PORTB Port B pin 8 selected for external interrupt 8 PORTC Port C pin 8 selected for external interrupt 8 PORTD...
Page 442 ...the world's most energy friendly microcontrollers Name Reset Access Description Set bit n to enable triggering of external interrupt n on falling edge. Value Description EXTIFALL[n] = 0 Falling edge trigger disabled EXTIFALL[n] = 1 Falling edge trigger enabled 28.5.14 GPIO_IEN - Interrupt Enable Register Offset Bit Position 0x110...
Page 443 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Description EXT[n] = 1 Pin n external interrupt flag set 28.5.16 GPIO_IFS - Interrupt Flag Set Register Offset Bit Position 0x118 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0.
Page 444 ...the world's most energy friendly microcontrollers 28.5.18 GPIO_ROUTE - I/O Routing Register Offset Bit Position 0x120 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) SWLOCATION I/O Location Decides the location of the SW pins.
Page 445 ...the world's most energy friendly microcontrollers 28.5.20 GPIO_LOCK - Configuration Lock Register Offset Bit Position 0x128 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 LOCKKEY 0x0000...
Page 446: Lcd - Liquid Crystal Display Driver
EM2 for long periods. Adding the flexible frame rate setting, contrast control, and different multiplexing modes make the EFM32G the optimal choice for battery-driven systems with LCD panels. 29.1 Introduction The LCD driver is capable of driving a segmented LCD display with up to 4x40 segments. A voltage boost function enables it to provide the LCD display with higher voltage than the supply voltage for the device.
Page 447: Functional Description
The LCD_SEGEN register determines which segment lines are enabled. Segment lines can be Each LCD segment pin can also be individually disabled by setting the pin to any other state than DISABLED in the GPIO pin configuration. Note that this feature is not available on EFM32G revisions A and B.
Page 448: Lcd Mux Settings
...the world's most energy friendly microcontrollers Table 29.1. LCD Mux Settings Mode Multiplexing Static Static (segments can be multiplexed with LCD_COM[0]) Duplex Duplex (segments can be multiplexed with LCD_COM[1:0]) Triplex Triplex (segments can be multiplexed with LCD_COM[2:0]) Quadruplex Quadruplex (segments can be multiplexed with LCD_COM[3:0]) Table 29.2.
Page 449 ...the world's most energy friendly microcontrollers 29.3.3.1 Waveforms with Static Bias and Multiplexing • With static bias and multiplexing, each segment line can be connected to LCD_COM0. When the segment line has the same waveform as LCD_COM0, the LCD panel pixel is turned off, while when the segment line has the opposite waveform, the LCD panel pixel is turned on.
Page 450: Lcd 1/2 Bias And Duplex Multiplexing - Lcd_Seg0
...the world's most energy friendly microcontrollers Figure 29.7. LCD 1/2 Bias and Duplex Multiplexing - LCD_SEG0 (1/ 2V Fram e Start Fram e End Figure 29.8. LCD 1/2 Bias and Duplex Multiplexing - LCD_SEG0 Connection com 0 com 1 1/2 bias and duplex multiplexing - LCD_SEG0-LCD_COM0 •...
Page 451 ...the world's most energy friendly microcontrollers Figure 29.10. LCD 1/2 Bias and Duplex Multiplexing - LCD_SEG0-LCD_COM1 (1/ 2V (1/ 2V Fram e Start Fram e End 29.3.3.3 Waveforms with 1/3 Bias and Duplex Multiplexing In this mode, each frame is divided into 4 periods. LCD_COM[1:0] lines can be multiplexed with all segment lines.
Page 452 ...the world's most energy friendly microcontrollers Figure 29.13. LCD 1/3 Bias and Duplex Multiplexing - LCD_SEG0 (2/ 3V (1/ 3V Fram e Start Fram e End Figure 29.14. LCD 1/3 Bias and Duplex Multiplexing - LCD_SEG0 Connection com 0 com 1 1/3 bias and duplex multiplexing - LCD_SEG0-LCD_COM0 •...
Page 453 ...the world's most energy friendly microcontrollers Figure 29.16. LCD 1/3 Bias and Duplex Multiplexing - LCD_SEG0-LCD_COM1 (2/ 3V (1/ 3V (1/ 3V (2/ 3V Fram e Start Fram e End 29.3.3.4 Waveforms with 1/2 Bias and Triplex Multiplexing In this mode, each frame is divided into 6 periods. LCD_COM[2:0] lines can be multiplexed with all segment lines.
Page 454 ...the world's most energy friendly microcontrollers Figure 29.20. LCD 1/2 Bias and Triplex Multiplexing - LCD_SEG0 (1/ 2V Fram e Start Fram e End Figure 29.21. LCD 1/2 Bias and Triplex Multiplexing - LCD_SEG0 Connection com 0 com 1 com 2 1/2 bias and triplex multiplexing - LCD_SEG0-LCD_COM0 •...
Page 455 ...the world's most energy friendly microcontrollers 1/2 bias and triplex multiplexing - LCD_SEG0-LCD_COM2 • DC voltage = 0 (over one frame) • V = 0.4 × V LCD_OUT • The LCD display pixel that is connected to LCD_SEG0 and LCD_COM2 will be OFF with this waveform Figure 29.24.
Page 456 ...the world's most energy friendly microcontrollers 1/3 bias and triplex multiplexing - LCD_SEG0 The LCD_SEG0 waveform illustrates how different segment waveforms can be multiplexed with the COM lines in order to turn on and off LCD pixels. As illustrated in the figures below, this waveform will turn ON pixels connected to LCD_COM1, while pixels connected to LCD_COM0 and LCD_COM2 will be turned OFF.
Page 457 ...the world's most energy friendly microcontrollers Figure 29.31. LCD 1/3 Bias and Triplex Multiplexing - LCD_SEG0-LCD_COM1 (2/ 3V (1/ 3V (1/ 3V (2/ 3V Fram e Start Fram e End 1/3 bias and triplex multiplexing - LCD_SEG0-LCD_COM2 • DC voltage = 0 (over one frame) •...
Page 458 ...the world's most energy friendly microcontrollers Figure 29.34. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_COM1 (2/ 3V (1/ 3V Fram e Start Fram e End Figure 29.35. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_COM2 (2/ 3V (1/ 3V Fram e Start Fram e End Figure 29.36.
Page 459 ...the world's most energy friendly microcontrollers Figure 29.38. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_SEG0 Connection com 0 com 1 com 2 com 3 1/3 bias and quadruplex multiplexing - LCD_SEG0-LCD_COM0 • DC voltage = 0 (over one frame) •...
Page 460: Lcd Contrast
...the world's most energy friendly microcontrollers Figure 29.41. LCD 1/3 Bias and Quadruplex Multiplexing - LCD_SEG0-LCD_COM2 (2/ 3V (1/ 3V (1/ 3V (2/ 3V Fram e Start Fram e End 1/3 bias and quadruplex multiplexing - LCD_SEG0-LCD_COM2 • DC voltage = 0 (over one frame) •...
Page 461: Lcd Contrast Function
...the world's most energy friendly microcontrollers Table 29.5. LCD Contrast Function CONCONF Function Contrast is adjusted relative to V Contrast is adjusted relative to Ground Table 29.6. LCD Principle of Contrast Adjustment for Different Bias Settings. Contrast adjustment Contrast adjustment No contrast adjustment relative to V relative to GND...
Page 462: Lcd
...the world's most energy friendly microcontrollers When using the voltage booster, the LCD_BEXT pin must be connected through a 1 µF capacitor to VSS, and the LCD_BCAP_P and LCD_BCAP_N pins must be connected to each other through a 22 nF capacitor. It is also possible to connect a dedicated power supply to the LCD module.
Page 463: Lcd Frame Rate Conversion Table
...the world's most energy friendly microcontrollers To use this module, the LE interface clock must be enabled in CMU_HFCORECLKEN0, in addition to the module clock. 29.3.7.2 Frame rate Division Register The frame rate is set in the CMU by programming the frame rate division bits FDIV in CMU_LCDCTRL. This setting should not be changed while the LCD driver is running.
Page 464: Fcpresc
...the world's most energy friendly microcontrollers 29.3.9 Frame Counter (FC) The Frame Counter is synchronized to the LCD frame start and will generate an event after a programmable number of frames. An FC event can trigger: • LCD ready interrupt •...
Page 465 ...the world's most energy friendly microcontrollers Figure 29.43. LCD Clock System in LCD Driver FDIV[2:0] div16 LFXO LFACLK div32 LCDpre LFACLK Counter div64 LFRCO LFACLK div128 LCD in CMU_LFAPRESC0 FCTOP[5:0] div2 static div1 div2 div4 LCD Fram e duplex EVENT triplex Counter div4...
Page 466: Lcd Animation Shift Register
...the world's most energy friendly microcontrollers Table 29.12. LCD Animation Shift Register AREGnSC, n = A Mode Description or B NOSHIFT No Shift operation SHIFTLEFT Animation register is shifted left (LCD_AREGA is shifted every odd state, LCD_AREGB is shifted every even state) SHIFTRIGHT Animation register is shifted right (LCD_AREGA is shifted every odd state, LCD_AREGB is shifted every even state)
Page 467 ...the world's most energy friendly microcontrollers In the table, AREGASC = 10, AREGBSC = 10, ALOGSEL = 1 and the resulting data is to be displayed on segment lines 7-0 multiplexed with LCD_COM0. Figure 29.44. LCD Block Diagram of the Animation Circuit SEGD0[7:0] AREGASC = 1 = >...
Page 468 ...the world's most energy friendly microcontrollers 29.3.13 Register access Since this module is a Low Energy Peripheral, and runs off a clock which is asynchronous to the HFCORECLK, special considerations must be taken when accessing registers. Please refer to Section 5.3 (p. 20) for a description on how to perform register accesses to Low Energy Peripherals. www.silabs.com 2014-07-02 - Gecko Family - d0001_Rev1.30...
Page 469: Register Map
...the world's most energy friendly microcontrollers 29.4 Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 LCD_CTRL Control Register 0x004 LCD_DISPCTRL Display Control Register 0x008 LCD_SEGEN Segment Enable Register 0x00C LCD_BACTRL Blink and Animation Control Register 0x010 LCD_STATUS...
Page 470 ...the world's most energy friendly microcontrollers Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) UDCTRL Update Data Control These bits control how data from the SEGDn registers are transferred to the LCD driver.
Page 471 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description LEVEL5 LEVEL6 LEVEL7 Maximum boost level Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) VLCDSEL Selection This bit controls which Voltage source that is connected to V Value Mode...
Page 472 ...the world's most energy friendly microcontrollers 29.5.3 LCD_SEGEN - Segment Enable Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) SEGEN 0x000 Segment Enable...
Page 473 ...the world's most energy friendly microcontrollers Name Reset Access Description Value Mode Description AREGA and AREGB OR'ed AREGBSC Animate Register B Shift Control These bits controls the shift operation that is performed on Animation register B. Value Mode Description NOSHIFT No Shift operation on Animation Register B SHIFTLEFT Animation Register B is shifted left...
Page 474 ...the world's most energy friendly microcontrollers Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) AREGA 0x00 Animation Register A Data This register contains the A data for generating animation pattern.
Page 475 ...the world's most energy friendly microcontrollers Name Reset Access Description Set when Frame Counter is zero. 29.5.9 LCD_IFS - Interrupt Flag Set Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) Frame Counter Interrupt Flag Set Write to 1 to set FC interrupt flag.
Page 476 ...the world's most energy friendly microcontrollers Name Reset Access Description Frame Counter Interrupt Enable Set to enable interrupt on frame counter interrupt flag. 29.5.12 LCD_SEGD0L - Segment Data Low Register 0 (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p. 20) . Offset Bit Position 0x040...
Page 477 ...the world's most energy friendly microcontrollers Offset Bit Position 0x048 Reset Access Name Name Reset Access Description 31:0 SEGD2L 0x00000000 COM2 Segment Data Low This register contains segment data for segment lines 0-31 for COM2. 29.5.15 LCD_SEGD3L - Segment Data Low Register 3 (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p.
Page 478 ...the world's most energy friendly microcontrollers Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) SEGD0H 0x00 COM0 Segment Data High This register contains segment data for segment lines 32-39 for COM0. 29.5.17 LCD_SEGD1H - Segment Data High Register 1 (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p.
Page 479 ...the world's most energy friendly microcontrollers Offset Bit Position 0x05C Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) SEGD3H 0x00 COM3 Segment Data High This register contains segment data for segment lines 32-39 for COM3.
Page 480 ...the world's most energy friendly microcontrollers Name Reset Access Description SEGD7L SEGD7L Register Busy Set when the value written to SEGD7L is being synchronized. SEGD6L SEGD6L Register Busy Set when the value written to SEGD6L is being synchronized. SEGD5L SEGD5L Register Busy Set when the value written to SEGD5L is being synchronized.
Page 481 ...the world's most energy friendly microcontrollers Offset Bit Position 0x0B4 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) SEGD4H 0x00 COM0 Segment Data High This register contains segment data for segment lines 32-39 for COM0.
Page 482 ...the world's most energy friendly microcontrollers Name Reset Access Description SEGD6H 0x00 COM2 Segment Data High This register contains segment data for segment lines 32-39 for COM2. 29.5.25 LCD_SEGD7H - Segment Data High Register 7 (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p. 20) . Offset Bit Position 0x0C0...
Page 483 ...the world's most energy friendly microcontrollers Offset Bit Position 0x0D0 Reset Access Name Name Reset Access Description 31:0 SEGD5L 0x00000000 COM5 Segment Data This register contains segment data for segment lines 0-23 for COM5. 29.5.28 LCD_SEGD6L - Segment Data Low Register 6 (Async Reg) For more information about Asynchronous Registers please see Section 5.3 (p.
Page 484 ...the world's most energy friendly microcontrollers Offset Bit Position 0x0D8 Reset Access Name Name Reset Access Description 31:0 SEGD7L 0x00000000 COM7 Segment Data This register contains segment data for segment lines 0-23 for COM7. www.silabs.com 2014-07-02 - Gecko Family - d0001_Rev1.30...
Page 485: Revision History
...the world's most energy friendly microcontrollers 30 Revision History 30.1 Revision 1.30 July 2nd, 2014 Updated current numbers and voltage supply range. Moved chapter "Device Revision" to section 3. 30.2 Revision 1.20 August 22nd, 2013 Fixed description of ADDRSET, RDSTRB, and WRSTRB fields in EBI Timing section. Corrected I2C pull-up resistor equation.
Page 486: Revision 1.00
...the world's most energy friendly microcontrollers Changed formula in VDDLEVEL bitfield in ACMPn_INPUTSEL. Added sine wave minimum amplitude to BUFEXTCLK. Changed description of IRQERASEABORT. Updated description of WARMUPMODE in ADC section. Fixed description for REFSEL field in CMU_CALCTRL. Fixed description of RXDATAV and TXBL interrupt flags in CMU. Added documentation for DMA_CHREQSTATUS, DMA_CHSREQSTATUS.
Page 487: Revision 0.84
...the world's most energy friendly microcontrollers Added Result Resolution column in Table 25.3 (p. 381) . Changed ADC calibration routines in Section 25.3.10 (p. 382) . Added table with ADC calibration register effect (Table 25.5 (p. 383) ). Improved ADC Input Filter description and added Figure 25.4 (p. 378) . Added minimum supply voltage restrictions when using the 2.5 V and 5 V bandgap references.
Page 488 ...the world's most energy friendly microcontrollers Updated DI table and moved to "Memory and Bus System" Section 5.6 (p. 23) . Updated Section 11.3.3.2 (p. 101) to include information about AUXHFRCO. EMU_ATESTCTRL register removed. AUX field in EMU_AUXCTRL renamed to HRCCLR and shrinked to 1 bit. All DMA channel registers split into separate bit fields.
Page 489: Revision 0.83
...the world's most energy friendly microcontrollers Enumeration of RES in ADCn_SCANCTRL changed. Changed access types for RH registers to R (read only). Enumeration of UDCTRL in LCD_CTRL changed. CH0EN in DACn_CH0CTRL renamed to EN. CH0REFREN in DACn_CH0CTRL renamed to REFFREN. CH0PRSEN in DACn_CH0CTRL renamed to PRSEN.
Page 490: Revision 0.82
...the world's most energy friendly microcontrollers Corrected DAC clock prescaling equation (Equation 26.1 (p. 399) ). 30.7 Revision 0.82 November 20th, 2009 Description of LFXOSEL and LFRCOSEL bits of CMU_STATUS register corrected. Updated description of EM4 sequence in Table 10.2 (p. 90) . Updated documentation of WORDTIMEOUT and WDATAREADY in MSC_STATUS.
Page 491: Abbreviations
...the world's most energy friendly microcontrollers A Abbreviations A.1 Abbreviations This section lists abbreviations used in this document. Table A.1. Abbreviations Abbreviation Description ACMP Analog Comparator Analog to Digital Converter AMBA Advanced High-performance Bus. AMBA is short for "Advanced Microcontroller Bus Architecture".
Page 492 ...the world's most energy friendly microcontrollers Abbreviation Description LEUART Low Energy Universal Asynchronous Receiver Transmitter LFRCO Low Frequency RC Oscillator LFXO Low Frequency Crystal Oscillator Low-speed Media Access Controller NVIC Nested Vector Interrupt Controller Oversampling Ratio On-the-go PCNT Pulse Counter Physical Layer Peripheral Reflex System Pulse Width Modulation...
Page 493: Disclaimer And Trademarks
A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications. Silicon Laboratories products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.
Page 494: Contact Information
...the world's most energy friendly microcontrollers C Contact Information Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Please visit the Silicon Labs Technical Support web page: http://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. www.silabs.com 2014-07-02 - Gecko Family - d0001_Rev1.30...
Page 495: Table Of Contents
...the world's most energy friendly microcontrollers Table of Contents 1. Energy Friendly Microcontrollers ........................2 1.1. Typical Applications ......................... 2 1.2. EFM32G Development ........................2 2. About This Document ..........................3 2.1. Conventions ........................... 3 2.2. Related Documentation ........................4 3.
Page 496 ...the world's most energy friendly microcontrollers 13.2. Features ..........................128 13.3. Functional Description ........................ 128 13.4. Register Map ..........................132 13.5. Register Description ........................132 14. EBI - External Bus Interface ........................136 14.1. Introduction ..........................136 14.2. Features ..........................136 14.3.
Page 497 ...the world's most energy friendly microcontrollers 25.4. Register Map ..........................384 25.5. Register Description ........................384 26. DAC - Digital to Analog Converter ......................397 26.1. Introduction ..........................397 26.2. Features ..........................397 26.3. Functional Description ........................ 398 26.4. Register Map ..........................403 26.5.
Page 498 ...the world's most energy friendly microcontrollers List of Figures 3.1. Block Diagram of EFM32G ........................7 3.2. Energy Mode Indicator ..........................7 3.3. Revision Number Extraction ........................10 4.1. Interrupt Operation ..........................12 5.1. EFM32G Bus System ..........................15 5.2. System Address Space .......................... 16 5.3.
Page 499 ...the world's most energy friendly microcontrollers 18.5. LEUART Local Loopback ........................257 18.6. LEUART Half Duplex Communication with External Driver ................. 258 18.7. LEUART - NRZ vs. RZI ........................259 19.1. TIMER Block Overview ........................276 19.2. TIMER Hardware Timer/Counter Control ....................277 19.3.
Page 500 ...the world's most energy friendly microcontrollers 29.11. LCD 1/3 Bias and Duplex Multiplexing - LCD_COM0 ................451 29.12. LCD 1/3 Bias and Duplex Multiplexing - LCD_COM1 ................451 29.13. LCD 1/3 Bias and Duplex Multiplexing - LCD_SEG0 ................452 29.14. LCD 1/3 Bias and Duplex Multiplexing - LCD_SEG0 Connection ............... 452 29.15.
Page 501 List of Tables 2.1. Register Access Types ..........................3 3.1. Energy Mode Description ......................... 8 3.2. EFM32G Microcontroller Series ......................... 8 3.3. Minor Revision Number Interpretation ....................... 10 4.1. Interrupt Request Lines (IRQ) ........................12 5.1. Memory System Core Peripherals ......................17 5.2.
Page 502 ...the world's most energy friendly microcontrollers 29.6. LCD Principle of Contrast Adjustment for Different Bias Settings..............461 29.7. LCD V ............................462 29.8. LCD V Frequency ........................462 BOOST 29.9. LCD Frame rate Conversion Table ......................463 29.10. LCD Update Data Control (UDCTRL) Bits ..................... 463 29.11.
Page 503 ...the world's most energy friendly microcontrollers List of Examples 8.1. DMA Transfer ............................61 16.1. USART Multi-processor Mode Example ....................221 19.1. TIMER DTI Example 1 ........................288 19.2. TIMER DTI Example 2 ........................288 21.1. LETIMER Triggered Output Generation ....................328 21.2.
Page 504 ...the world's most energy friendly microcontrollers List of Equations 5.1. Memory SRAM Area Set/Clear Bit ......................16 5.2. Memory Peripheral Area Bit Modification ....................17 5.3. Memory Wait Cycles with Clock Equal or Faster than HFCORECLK ............... 20 5.4. Memory Wait Cycles with Clock Slower than CPU ..................20 12.1.

Silicon Laboratories EFM32G Reference Manual

Table of Contents

1 Energy Friendly Microcontrollers

2 About this Document

3 System Overview

4 System Processor

5 Memory and Bus System

6 DBG - Debug Interface

7 MSC - Memory System Controller

8 DMA - DMA Controller

9 RMU - Reset Management Unit

10 EMU - Energy Management Unit

11 CMU - Clock Management Unit

12 WDOG - Watchdog Timer

13 PRS - Peripheral Reflex System

14 EBI - External Bus Interface

100 C - Inter-Integrated Circuit Interface

16 USART - Universal Synchronous Asynchronous Receiver/Transmitter

17 UART - Universal Asynchronous Receiver/Transmitter

18 LEUART - Low Energy Universal Asynchronous Receiver/Transmitter

19 TIMER - Timer/Counter

20 RTC - Real Time Counter

21 LETIMER - Low Energy Timer

22 PCNT - Pulse Counter

23 ACMP - Analog Comparator

24 VCMP - Voltage Comparator

25 ADC - Analog to Digital Converter

26 DAC - Digital to Analog Converter

27 AES - Advanced Encryption Standard Accelerator

28 GPIO - General Purpose Input/Output

29 LCD - Liquid Crystal Display Driver

30 Revision History

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