Daewoo DSL-19M1WC Service Manual page 21

Table 8: Parallel/Serial ROM Interface
Pin Name No
A17 95
A16 96
A15 100
A14 101
A13 102
A12 103
A11 104
A10 105
A9 106
A8 107
A7 108
A6 109
A5 110
A4 111
A3 112
A2 113
A1 114
A0 115
D7 132
D6 131
D5 130
D4 129
D3 128
D2 125
D1 124
D0 123
ROM_OEN 118
ROM_SDI/ ROM_WEN 97
ROM_SCSN/ ROM_CSN 94
Table 9: Digital Power and Ground
Pin Name No
RVDD_3.3 32 49 98 116 154
CVDD_1.8 18 28 39 45 84 119 126 133 143
CRVSS 19 29 33 40 46 50 85 99 117 120
127 134 144 155
Table 10: JTAG Boundary Scan
Pin Name No I/O Description
TCK 34 I JTAG Boundary Scan TCK signal
TDO 55 O JTAG Boundary Scan TDO signal
TDI 35 I JTAG Boundary Scan TDI signal. Pad has internal 50K pull-up resistor.
TMS 36 I JTAG Boundary Scan RST signal. Pad has internal 50K pull-up resistor.
TRST 37 I JTAG Boundary Scan TMS signal. Pad has internal 50K pull-up resistor.
Single P-Channel Enhancement Mode Field Effect Transistor
3. FDS9435A
SO-8 P-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high
cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance and
provide superior switching performance. These devices are particularly suited for low voltage applications such as
notebook computer power management and other battery powered circuits where fast switching, low in-line power loss,
and resistance to transients are needed.
· Features
-5.3 A, -30 V, R
DS(ON)
I/O Description
O 256K x8 PROM Address. These pins also have bootstrap functionality.
For serial SPI ROM interface:
- ROM_ADDR17 will be Serial Clock (ROM_SCLK)
- ROM_ADDR16 will be Serial Data Output (ROM_SDO)
For 512K X 8 PROM, Address Signal A18 is available thru Pin # 44 which is GPIO10.
IO External PROM data input.
O External PROM data Output Enable.
O External PROM data Write Enable (for In-System-Programming of FLASH) or Serial Data Input (SDI) for SPI ROM interface.
O External PROM data Chip Select or Serial PROM Chip Select (ROM_SCSN) for SPI ROM interface.
I/O
P
P
G
= 0.045 Ω @ V = -10 V,
GS
Description
Ring VDD. Connect to digital 3.3V.
Core VDD. Connect to digital 1.8V.
Chip ground for core and ring.
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