Introduction; Key Points For Optimal Layout - Renesas P9235A-RB Layout Manual

1. Introduction

The P9235A-RB Wireless Power Receiver (Tx) is an integrated circuit (IC) consisting of multiple high-power blocks and noise-sensitive
circuits controlled by a microprocessor. When implementing the application circuit on a printed circuit board (PCB), there are often tradeoffs
associated with managing the critical current paths. To optimize the design, place components on the circuit board based on circuit function to
guarantee best performance. The thermal management of the P9235A-RB is also important to the product's performance and should be
optimized when designing the PCB. Use the following guidance to place the components in order of priority based on operation.
There are three main categories of circuitry:
Power circuits

Sensitive circuits

Non-sensitive circuits


Key Points for Optimal Layout

Route the power connections wide and on the same side of the PCB as the P9235A-RB (≥ 100mils).

Use the layer under the P9235A-RB side of the board as a solid ground plane.

Connect the exposed thermal pad (EP) in the center of the P9235A-RB to all other layers with an array of 4x5 10 mil vias.

Avoid unnecessary layer transitions of the AC power connections (LC node, LC tank driving FETs, and GND).

Place the P9235A-RB as close as possible to the center of the board. Avoid placing it along the PCB edge.

Connect as much copper as possible to every pin of the P9235A-RB, including pins that do not carry high current.

Use low ESR resonance capacitors (Cs/Cd) to decrease losses in the LC and AC1 current path (C0G preferred).

Place components in the following order:

POWER CIRCUITS – NON H BRIDGE POWER STAGE:
•
CIN, CBOOST: Place all IC pin input voltage capacitors and boost capacitors close to their related pins (V

VDDIO, BST_BRG1, BST_BRG2, DRV_ V
Buck Regulator L, Cout: Place the inductor as close as possible to the switch node pin to reduce the switching noise of that node.

Place the buck regulator inductance and output capacitance such that they form the smallest possible current loop to minimize
EMI transmissions.
SENSITIVE CIRCUITS – VOLTAGE AND CURRENT MEASUREMENT:
•
Current Sense: Place the bridge input current sense resistor directly in the current path to the tank FET drivers. Place the filtering

components close to the sense resistor and tightly together.
Current Demodulation: Place the current demodulation circuit components tightly together and close to their related IC pins

(ISNS_OUT, IDEMI).
Voltage Demodulation: Place the voltage demodulation circuit components tightly together and close to their related IC pin

(VDEM1).
POWER CIRCUITS – H BRIDGE POWER STAGE:
•
H Bridge: Place H bridge FETs (Q5, Q7) and LC tank capacitance (C44, C47, C48, C49) close to each other, to form a small current

loop, to avoid EMI emissions.
H Bridge Cin: Place the V_BRG FET-H-Bridge capacitors such that the traces are short. This is the large DC and AC current path.

SENSITIVE CIRCUITS – FET GATE DRIVER COMPONENTS:
•
Gate driver circuit: Place the Low Side FET Gate and High Side Gate Rs close to their respective pins (GH_BRG1, 2, GL_BRG1, 2)

and connect the Output RC Snubbers directly onto their respective the H Bridge switch nodes.
Gate driver traces: Avoid running under the H Bridge switch nodes. Run these traces under the relatively quiet VBRG node instead.

Place a ground layer between these traces and the top signal level. Surround these traces with the ground plane to provide a
tight loop AC signal return path to avoid EMI noise.
© 2019 Integrated Device Technology, Inc
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P9235A-RB Layout Guide
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IN
March 19, 2019