I 2 C Serial Microprocessor Interface; Figure 32. I 2 C Command Format; Figure 33. I2C Example - Silicon Laboratories Si5328 Family Reference Manual

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6.13. I C Serial Microprocessor Interface
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When configured in I C control mode (CMODE = L), the control interface to the device is a 2-wire bus for
bidirectional communication. The bus consists of a bidirectional serial data line (SDA) and a serial clock input
(SCL). Both lines must be connected to the positive supply via an external pull-up. In addition, an output interrupt
(INT) is provided with selectable active polarity (determined by INT_POL bit). Fast mode operation is supported for
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transfer rates up to 400 kbps as specified in the I C-Bus Specification standard. To provide bus address flexibility,
three pins (A[2:0]) are available to customize the LSBs of the device address. The complete bus address for the
device is as follows:
1 1 0 1 A[2] A[1] A[0] R/W.
Figure 32 shows the command format for both read and write access. Data is always sent MSB first. The timing
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specifications and timing diagram for the I C bus can be found in the I C-Bus Specification standard (fast mode
operation) (See: http://www.standardics.nxp.com/literature/books/i2c/pdf/i2c.bus.specification.pdf).
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The maximum I C clock speed is 400 kHz.
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Figure 32. I C Command Format
In Figure 33, the value 68 is seven bits. The sequence of the example is: Write register 00 with the value 0xAA;
then, read register 00. Note that 0 = Write = W, and 1 = Read = R.
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Figure 33. I C Example
90 Rev. 1.3