Silicon Laboratories Si5324 Manual
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Silicon Laboratories Si5324 Manual

Any-frequency precision clock multiplier/jitter attenuator
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Features
Generates any frequency from 2 kHz to 945 MHz
and select frequencies to 1.4 GHz from an input
frequency of 2 kHz to 710 MHz
Ultra-low jitter clock outputs as low as 290 fs rms
(12 kHz–20 MHz), 320 fs rms (50 kHz–80 MHz)
Integrated loop filter with selectable loop bandwidth
(4– 525 Hz)
Meets ITU-T G.8251 and Telcordia GR-253-CORE
jitter specification
Hitless input clock switching with phase build-out
Freerun, Digital Hold operation
Applications
Broadcast video –3G/HD/SD-SDI, Genlock
Packet Optical Transport Systems (P-OTS), MSPP
OTN OTU-1/2/3/4 Asynchronous Demapping
(Gapped Clock)
SONET OC-48/192/768, SDH/STM-16/64/256 line
cards
Description
The Si5324 is a low-bandwidth, jitter-attenuating, precision clock multiplier for applications requiring sub 1 ps jitter
performance with loop bandwidths between 4 Hz and 525 Hz. The Si5324 accepts two input clocks ranging from
2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz to 945 MHz and select frequencies to
1.4 GHz. The two outputs are divided down separately from a common source. The Si5324 can also use its
external reference as a clock source for frequency synthesis. The device provides virtually any frequency
translation combination across this operating range. The Si5324 input clock frequency and clock multiplication ratio
are programmable via an I
®
DSPLL
technology, which provides any-frequency synthesis and jitter attenuation in a highly integrated PLL
solution that eliminates the need for external VCXO and filter components. The DSPLL loop bandwidth is digitally
programmable, providing jitter performance optimization at the application level. The Si5324 is ideal for providing
clock multiplication and jitter attenuation in high performance timing applications.
Preliminary Rev. 0.3 11/10
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
2
C or SPI interface. The Si5324 is based on Silicon Laboratories' 3rd-generation
Copyright © 2010 by Silicon Laboratories
A
-F
N Y
REQUENCY
M
/J
U L T I P L I E R
Configurable signal format per output (LVPECL,
LVDS, CML, CMOS)
Support for ITU G.709 and custom FEC ratios
(255/238, 255/237, 255/236, 239/237, 66/64,
239/238, 15/14, 253/221, 255/238)
LOL, LOS, FOS alarm outputs
2
I
C or SPI programmable
On-chip voltage regulator with high PSNR
Single supply 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%
Small size: 6 x 6 mm 36-lead QFN
1/2/4/8/10G Fibre Channel line cards
GbE/10/40/100G Synchronous Ethernet
(LAN/WAN)
Data converter clocking
Wireless base stations
Test and measurement
Si5324
P
C
RE CISION
L O C K
A
I T T E R
TTE NU A T OR
Si5324

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Summary of Contents for Silicon Laboratories Si5324

  • Page 1 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The two outputs are divided down separately from a common source. The Si5324 can also use its external reference as a clock source for frequency synthesis.
  • Page 2 Si5324 Functional Block Diagram Xtal or Refclock ÷ N31 CKIN1 ÷ NC1_LS CKOUT1 ® CKIN2 ÷ N32 DSPLL ÷ N1_HS ÷ NC2_LS CKOUT2 Xtal/Refclock ÷ N2 Loss of Signal/ VDD (1.8, 2.5, or 3.3 V) Frequency Offset Control Signal Detect...

  • Page 3: Table Of Contents

    4. Pin Descriptions: Si5324 ........

  • Page 4: Electrical Specifications

    — Notes: 1. For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Frequency Precision Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing. 2. This is the amount of leakage that the 3-level input can tolerate from an external driver. See the Family Reference Manual.
  • Page 5 Case to Ambient Notes: 1. For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Frequency Precision Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing. 2. This is the amount of leakage that the 3-level input can tolerate from an external driver. See the Family Reference Manual.
  • Page 6 Si5324 Table 2. Absolute Maximum Ratings Parameter Symbol Test Condition Unit DC Supply Voltage –0.5 — LVCMOS Input Voltage –0.3 +0.3 CKINn Voltage Level Limits — XA/XB Voltage Level Limits — Operating Junction Temperature –55 — ºC Storage Temperature Range –55...

  • Page 7: Typical Phase Noise Performance

    Si5324 2. Typical Phase Noise Performance Figure 1. Broadcast Video Jitter Bandwidth Jitter (peak-peak) Jitter (RMS) 10 Hz to 20 MHz 5.24 ps Note: Number of samples: 8.91E9 Preliminary Rev. 0.3...
  • Page 8 Si5324 Figure 2. OTN/SONET/SDH Phase Noise Note: Phase noise plot uses brick wall integration. Jitter Bandwidth Jitter, RMS SONET_OC48, 12 kHz to 20 MHz 266 fs SONET_OC192_A, 20 kHz to 80 MHz 283 fs SONET_OC192_B, 4 MHz to 80 MHz...
  • Page 9 Si5324 Figure 3. Wireless Base Station Phase Noise Jitter Bandwidth Jitter (peak-peak) Jitter (RMS) 10 Hz to 20 MHz 7.28 ps Note: Number of samples: 8.91E9 Preliminary Rev. 0.3...
  • Page 10 Reset 1. Assumes differential LVPECL termination (3.3 V) on clock inputs. Notes: 2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD). Figure 5. Si5324 Typical Application Circuit (SPI Control Mode) Preliminary Rev. 0.3...

  • Page 11: Functional Description

    The The Si5324 supports hitless switching between the two Si5324 accepts two input clocks ranging from 2 kHz to synchronous input clocks in compliance with Telcordia 710 MHz and generates two output clocks ranging from GR-253-CORE that greatly minimizes the propagation 2 kHz to 945 MHz and select frequencies to 1.4 GHz.

  • Page 12: External Reference

    For example, with a 20 ppm oscillator as the reference on the XA/XB pins, temperature changes cause the oscillator to change frequency slightly. Although the Si5324 is locked to its input on CLKIN, it also uses the XA/XB as a reference.

  • Page 13: Pin Descriptions: Si5324

    0 = CKIN2 present. 1 = LOS (FOS) on CKIN2. The active polarity can be changed by CK_BAD_POL. If CK2_BAD_PIN = 0, the pin tristates. Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5324 Register Map. Preliminary Rev. 0.3...
  • Page 14 If LOL_PIN = 0, this pin will tristate. Active polarity is controlled by the LOL_POL bit. The PLL lock status will always be reflected in the LOL_INT read only register bit. Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5324 Register Map. Preliminary Rev. 0.3...
  • Page 15 C control mode (CMODE = 0), this pin is ignored. In SPI control mode (CMODE = 1), this pin functions as the serial data input. This pin has a weak pull-down. Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5324 Register Map. Preliminary Rev. 0.3...
  • Page 16 This pin must not be NC. Tie either high or low. Ground Pad. GND PAD Supply The ground pad must provide a low thermal and electrical impedance to a ground plane. Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5324 Register Map. Preliminary Rev. 0.3...

  • Page 17: Register Map

    Si5324 5. Register Map All register bits that are not defined in this map should always be written with the specified Reset Values. The writing to these bits of values other than the specified Reset Values may result in undefined device behavior.
  • Page 18 Si5324 Register N32[15:8] N32[7:0] CLKIN2RATE[2:0] CLKIN1RATE[2:0] CK2_ACTV_REG CK1_ACTV_REG LOS2_INT LOS1_INT LOSX_INT DIGHOLD- FOS2_INT FOS1_INT LOL_INT VALID LOS2_FLG LOS1_FLG LOSX_FLG FOS2_FLG FOS1_FLG LOL_FLG PARTNUM_RO[11:4] PARTNUM_RO[3:0] REVID_RO[3:0] RST_REG ICAL FASTLOCK LOS2_EN [1:1] LOS1_EN [1:1] LOS2_EN[0:0] LOS1_EN[0:0] FOS2_EN FOS1_EN INDEPENDENTSKEW1[7:0] INDEPENDENTSKEW2[7:0] NVM_REVID[7:0] Table 3. CKOUT_ALWAYS_ON and SQ_ICAL Truth Table...

  • Page 19: Register Descriptions

    Si5324 6. Register Descriptions Register 0. Name FREE_RUN CKOUT_ BYPASS_ ALWAYS_ON Type Reset value = 0001 0100 Name Function Reserved Reserved. FREE_RUN Free Run. Internal to the device, route XA/XB to CKIN2. This allows the device to lock to its XA-XB reference.
  • Page 20 Si5324 Register 1. Name Reserved CK_PRIOR2 [1:0] CK_PRIOR1 [1:0] Type Reset value = 1110 0100 Name Function Reserved Reserved. CK_PRIOR2 CK_PRIOR 2. [1:0] Selects which of the input clocks will be 2nd priority in the autoselection state machine. 00: CKIN1 is 2nd priority.
  • Page 21 Si5324 Register 3. Name CKSEL_REG [1:0] DHOLD SQ_ICAL Reserved Type Reset value = 0000 0101 Name Function CKSEL_REG CKSEL_REG. [1:0] If the device is operating in register-based manual clock selection mode (AUTOSEL_REG = 00), and CKSEL_PIN = 0, then these bits select which input clock will be the active input clock.
  • Page 22 Si5324 Register 4. Name AUTOSEL_REG [1:0] Reserved HIST_DEL [4:0] Type Reset value = 0001 0010 Name Function AUTOSEL_ AUTOSEL_REG [1:0] REG [1:0] Selects method of input clock selection to be used. 00: Manual (either register or pin controlled, see CKSEL_PIN)
  • Page 23 Si5324 Register 6. Name Reserved SLEEP SFOUT2_REG [2:0] SFOUT1_REG [2:0] Type Reset value = 0010 1101 Name Function Reserved Reserved. SLEEP SLEEP. In sleep mode, all clock outputs are disabled and the maximum amount of internal cir- cuitry is powered down to reduce power dissipation and noise generation. This bit over- rides the SFOUTn_REG[2:0] output signal format settings.
  • Page 24 Si5324 Register 7. Name Reserved FOSREFSEL [2:0] Type Reset value = 0010 1010 Name Function Reserved. Reserved. FOSREFSEL FOSREFSEL [2:0]. [2:0] Selects which input clock is used as the reference frequency for Frequency Off-Set (FOS) alarms. 000: XA/XB (External reference)
  • Page 25 Si5324 Register 8. Name HLOG_2[1:0] HLOG_1[1:0] Reserved Type Reset value = 0000 0000 Name Function HLOG_2 [1:0] HLOG_2 [1:0]. 00: Normal operation 01: Holds CKOUT2 output at static logic 0. Entrance and exit from this state will occur without glitches or runt pulses.
  • Page 26 Si5324 Register 10. Name Reserved DSBL2_ DSBL1_ Reserved Type Reset value = 0000 0000 Name Function Reserved Reserved. DSBL2_REG DSBL2_REG. This bit controls the powerdown of the CKOUT2 output buffer. If disable mode is selected, the NC2 output divider is also powered down.
  • Page 27 Si5324 Register 19. Name FOS_EN FOS_THR [1:0] VALTIME [1:0] LOCKT [2:0] Type Reset value = 0010 1100 Name Function FOS_EN FOS_EN. Frequency Offset Enable globally disables FOS. See the individual FOS enables (FOSx_EN, register 139). 0: FOS disable 1: FOS enabled by FOSx_EN FOS_THR [1:0] FOS_THR [1:0].
  • Page 28 Si5324 Register 20. Name Reserved CK2_BAD_PIN CK1_BAD_PIN LOL_PIN INT_PIN Type Reset value = 0011 1110 Name Function Reserved Reserved. CK2_BAD_PIN CK2_BAD_PIN. The CK2_BAD status can be reflected on the C2B output pin. 0: C2B output pin tristated 1: C2B status reflected to output pin CK1_BAD_PIN CK1_BAD_PIN.
  • Page 29 Si5324 Register 21. Name Reserved CK1_ACTV_PIN CKSEL_ PIN Type Reset value = 1111 1111 Name Function Reserved Reserved. CK1_ACTV_PIN CK1_ACTV_PIN. The CK1_ACTV_REG status bit can be reflected to the CS_CA output pin using the CK1_ACTV_PIN enable function. CK1_ACTV_PIN is of consequence only when pin controlled clock selection is being used.
  • Page 30 Si5324 Register 22. Name Reserved CK_ACTV_POL CK_BAD_ POL LOL_POL INT_POL Type Reset value = 1101 1111 Name Function Reserved Reserved. CK_ACTV_ POL CK_ACTV_POL. Sets the active polarity for the CS_CA signals when reflected on an output pin. 0: Active low...
  • Page 31 Si5324 Register 23. Name Reserved LOS2_ MSK LOS1_ MSK LOSX_ MSK Type Reset value = 0001 1111 Name Function Reserved Reserved. LOS2_MSK LOS2_MSK. Determines if a LOS on CKIN2 (LOS2_FLG) is used in the generation of an interrupt. Writes to this register do not change the value held in the LOS2_FLG register.
  • Page 32 Si5324 Register 24. Name Reserved FOS2_MSK FOS1_MSK LOL_MSK Type Reset value = 0011 1111 Name Function Reserved Reserved. FOS2_MSK FOS2_MSK. Determines if the FOS2_FLG is used to in the generation of an interrupt. Writes to this register do not change the value held in the FOS2_FLG register.
  • Page 33 Si5324 Register 25. Name N1_HS [2:0] Reserved Type Reset value = 0010 0000 Name Function N1_HS [2:0] N1_HS [2:0]. Sets value for N1 high speed divider which drives NCn_LS (n = 1 to 2) low-speed divider. 000: N1= 4 001: N1= 5...
  • Page 34 Si5324 Register 32. Name NC1_LS [15:8] Type Reset value = 0000 0000 Name Function NC1_LS NC1_LS [15:8]. [15:8] Sets value for NC1 low-speed divider, which drives CKOUT1 output. Must be 0 or odd. 00000000000000000000 = 1 00000000000000000001 = 2 00000000000000000011 = 4...
  • Page 35 Si5324 Register 34. Name Reserved NC2_LS [19:16] Type Reset value = 0000 0000 Name Function Reserved Reserved. NC2_LS NC2_LS [19:16]. [19:16] Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must be 0 or odd. 00000000000000000000=1 00000000000000000001=2 00000000000000000011=4 00000000000000000101=6 11111111111111111111=2^20 Valid divider values=[1, 2, 4, 6, ..., 2^20]...
  • Page 36 Si5324 Register 36. Name NC2_LS [7:0] Type Reset value = 0011 0001 Name Function NC2_LS [7:0] NC2_LS [7:0]. Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must be 0 or odd. 00000000000000000000 = 1 00000000000000000001 = 2 00000000000000000011 = 4...
  • Page 37 Si5324 Register 40. Name N2_HS [2:0] Reserved N2_LS [19:16] Type Reset value = 1100 0000 Name Function N2_HS [2:0] N2_HS [2:0]. Sets value for N2 high speed divider which drives N2LS low-speed divider. 000: 4 001: 5 010: 6 011: 7...
  • Page 38 Si5324 Register 41. Name N2_LS [15:8] Type Reset value = 0000 0000 Name Function N2_LS [15:8] N2_LS [15:8]. Sets value for N2 low-speed divider, which drives phase detector. 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 11111111111111111111 = 2 Valid divider values = [2, 4, 6, ..., 2...
  • Page 39 Si5324 Register 43. Name Reserved N31 [18:16] Type Reset value = 0000 0000 Name Function Reserved Reserved. N31 [18:16] N31 [18:16]. Sets value for input divider for CKIN1. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 1111111111111111111 = 2 Valid divider values = [1, 2, 3, ..., 2...
  • Page 40 Si5324 Register 45. Name N31_[7:0] Type Reset value = 0000 1001 Name Function N31_[7:0 N31_[7:0]. Sets value for input divider for CKIN1. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 1111111111111111111 = 2 Valid divider values = [1, 2, 3, ..., 2 Register 46.
  • Page 41 Si5324 Register 47. Name N32_[15:8] Type Reset value = 0000 0000 Name Function N32_[15:8] N32_[15:8]. Sets value for input divider for CKIN1. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 1111111111111111111 = 2 Valid divider values = [1, 2, 3, ..., 2 Register 48.
  • Page 42 Si5324 Register 55. Name Reserved CLKIN2RATE_[2:0] CLKIN1RATE[2:0] Type Reset value = 0000 0000 Name Function Reserved Reserved. CLKIN2RATE[2:0] CLKIN2RATE_[2:0]. CKINn frequency selection for FOS alarm monitoring. 000: 10–27 MHz 001: 25–54 MHz 002: 50–105 MHz 003: 95–215 MHz 004: 190–435 MHz 005: 375–710 MHz...
  • Page 43 Si5324 Register 128. Name Reserved CK2_ACTV_REG CK1_ACTV_REG Type Reset value = 0010 0000 Name Function Reserved Reserved. CK2_ACTV_REG CK2_ACTV_REG. Indicates if CKIN2 is currently the active clock for the PLL input. 0: CKIN2 is not the active input clock. Either it is not selected or LOS2_INT is 1.
  • Page 44 Si5324 Register 130. Name Reserved DIGHOLDVALID Reserved FOS2_INT FOS1_INT LOL_INT Type Reset value = 0000 0001 Name Function DIGHOLDVALID Digital Hold Valid. Indicates if the digital hold circuit has enough samples of a valid clock to meet dig- ital hold specifications.
  • Page 45 Si5324 Register 131. Name Reserved LOS2_FLG LOS1_FLG LOSX_FLG Type Reset value = 0001 1111 Name Function Reserved Reserved. LOS2_FLG CKIN2 Loss-of-Signal Flag. 0: Normal operation. 1: Held version of LOS2_INT. Generates active output interrupt if output interrupt pin is enabled (INT_PIN = 1) and if not masked by LOS2_MSK bit. Flag cleared by writing 0 to this bit.
  • Page 46 Si5324 Register 132. Name Reserved FOS2_FLG FOS1_FLG LOL_FLG Reserved Type Reset value = 0000 0010 Name Function 7:4, 0 Reserved Reserved. FOS2_FLG CLKIN_2 Frequency Offset Flag. 0: Normal operation. 1: Held version of FOS2_INT. Generates active output interrupt if output interrupt pin is enabled (INT_PIN = 1) and if not masked by FOS2_MSK bit.
  • Page 47 Register 134. Name PARTNUM_RO [11:4] Type Reset value = 0000 0001 Name Function PARTNUM_RO [11:0] Device ID (1 of 2). 0000 0001 1000: Si5324 Others Reserved Register 135. Name PARTNUM_RO [3:0] REVID_RO [3:0] Type Reset value = 1010 0010 Name...
  • Page 48 Si5324 Register 136. Name RST_REG ICAL Reserved Type Reset value = 0000 0000 Name Function RST_REG Internal Reset (Same as Pin Reset). Note: The I2C (or SPI) port may not be accessed until 10 ms after RST_REG is asserted. 0: Normal operation.
  • Page 49 Si5324 Register 137. Name Reserved FASTLOCK Type Reset value = 0000 0000 Name Function Reserved Do not modify. FASTLOCK This bit must be set to 1 to enable FASTLOCK. This improves initial lock time by dynamically changing the loop bandwidth.
  • Page 50 Si5324 Register 139. Name Reserved LOS2_EN [0:0] LOS1_EN [0:0] Reserved FOS2_EN FOS1_EN Type Reset value = 1111 1111 Name Function 7:6, Reserved Reserved. LOS2_EN [1:0] Enable CKIN2 LOS Monitoring on the Specified Input (2 of 2). Note: LOS2_EN is split between two registers.
  • Page 51 Si5324 Register 142. Name INDEPENDENTSKEW1 [7:0] Type Reset value = 0000 0000 Name Function INDEPENDENTSKEW1 [7:0] INDEPENDENTSKEW1. 8 bit field that represents a twos complement of the phase offset in terms of clocks from the high speed output divider. Default = 0.

  • Page 52: Ical

    Si5324 6.1. ICAL The device's registers must be configured for the intended applications. After the part is configured, the part must perform a calibration procedure when there is a stable clock on the selected CLKINn input. The calibration process is triggered by writing a "1" to bit D6 in register 136. See the Family Reference Manual for details. In addition, after a successful calibration operation, changing any of the Registers indicated in Table 4 requires that a calibration be performed again by the same procedure (writing a "1"...

  • Page 53: Ordering Guide

    Si5324 7. Ordering Guide Ordering Part Output Clock Frequency Package ROHS6, Temperature Range Number Range Pb-Free Si5324A-C-GM 2 kHz–945 MHz 36-Lead 6 x 6 mm QFN –40 to 85 °C 970–1134 MHz 1.213–1.417 GHz Si5324B-C-GM 2 kHz–808 MHz 36-Lead 6 x 6 mm QFN –40 to 85 °C...
  • Page 54 Si5324 Table 5. Product Selection Guide Any-Frequency Precision Clock Multipliers (Wideband. Bandwidth: 30 kHz to 13 MHz))  Si5322 1050 0.6 ps rms typ    Si5325 1400 0.6 ps rms typ   Si5365 1050 0.6 ps rms typ ...

  • Page 55: Package Outline: 36-Pin Qfn

    Si5324 8. Package Outline: 36-Pin QFN Figure 7 illustrates the package details for the Si5324. Table 6 lists the values for the dimensions shown in the illustration. Figure 7. 36-Pin Quad Flat No-lead (QFN) Table 6. Package Dimensions Symbol Millimeters...

  • Page 56: Recommended Pcb Layout

    Si5324 9. Recommended PCB Layout Figure 8. PCB Land Pattern Diagram Figure 9. Ground Pad Recommended Layout Preliminary Rev. 0.3...
  • Page 57 Si5324 Table 7. PCB Land Pattern Dimensions Dimension 0.50 BSC. 5.42 REF. 5.42 REF. 4.00 4.20 4.00 4.20 4.53 — 4.53 — — 0.28 0.89 REF. — 6.31 — 6.31 Notes (General): 1. All dimensions shown are in millimeters (mm) unless otherwise noted.

  • Page 58: Si5324 Device Top Mark

    Si5324 10. Si5324 Device Top Mark Mark Method: Laser Font Size: 0.80 mm Right-Justified Line 1 Marking: Si5324Q Customer Part Number Q = Speed Code: A, B, C, D See Ordering Guide for options. Line 2 Marking: C-GM C = Product Revision G = Temperature Range –40 to 85 °C (RoHS6)

  • Page 59: Document Change List

    Si5324 OCUMENT HANGE Revision 0.1 to Revision 0.2  Updated Rise/Fall Time values.  Updated minimum loop BW value. Revision 0.2 to Revision 0.25  Updated features and applications.  Changed maximum loop bandwidth to 525 Hz (global).  Updated PLL performance specifications in Table 1.

  • Page 60: Contact Information

    Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per- sonal injury or death may occur.
  • Page 61 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Silicon Laboratories SI5324A-C-GMR SI5324B-C-GMR SI5324D-C-GMR Si5324A-C-GM Si5324B-C-GM Si5324C-C-GM Si5324D-C-...

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