Silicon Laboratories Si5316 Series Reference Manual
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Silicon Laboratories Si5316 Series Reference Manual

Silicon Laboratories Si5316 Series Reference Manual

Any-rate precision clocks
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A
- R
P
C
NY
ATE
RECISION
L O C K S
Si5316, Si5319,Si5322, Si5323, S
5 3 2 4 , S i 5 3 2 5 ,
I
Si5326, Si5365, Si5366, Si5367, Si5368
F
R
M
AMILY
EFERENCE
ANUAL
Rev. 0.41 10/09
Copyright © 2009 by Silicon Laboratories
Si53xx-RM
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

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  • Page 1 5 3 2 4 , S i 5 3 2 5 , Si5326, Si5365, Si5366, Si5367, Si5368 AMILY EFERENCE ANUAL Rev. 0.41 10/09 Copyright © 2009 by Silicon Laboratories Si53xx-RM This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
  • Page 2 Si53xx-RM Rev. 0.41...

  • Page 3: Table Of Contents

    Si53xx-RM ABLE O F ONTENTS Section Page 1. Any-Rate Precision Clock Product Family Overview ......11 1.1.
  • Page 4 Si53xx-RM 6.4.2. Recovery from Digital Hold (Si5316, Si5323, Si5366) ....... . 67 6.4.3.
  • Page 5 Si53xx-RM 7.8. Frame Synchronization Realignment (Si5368 and CK_CONFIG_REG = 1) ..92 7.8.1. FSYNC Realignment (Si5368) ..........94 7.8.2.
  • Page 6 Si53xx-RM I S T OF IGURES 1. Any-Rate Precision Clock Product Family Overview 2. Narrowband Versus Wideband Overview 3. Any-Rate Clock Family Members Figure 1. Si5316 Jitter Attenuator Block Diagram ........14 Figure 2.
  • Page 7 Si53xx-RM Figure 36. Typical Output Circuit (Not CMOS) ........108 Figure 37.
  • Page 8 Si53xx-RM I S T OF ABLES 1. Any-Rate Precision Clock Product Family Overview Table 1. Product Selection Guide ..........11 2.
  • Page 9 Si53xx-RM Table 35. Device Control Modes ..........72 Table 36.
  • Page 10 Si53xx-RM Table 72. Si5365 Pullup/down..........142 Table 73.

  • Page 11: Any-Rate Precision Clock Product Family Overview

    HDTV, test & measurement, data acquisition systems, and FPGA/ASIC reference clocking. Table 1 provides a product selector guide for the Silicon Laboratories Any-Rate Precision Clocks. Two product families are available. The Si5316, Si5319, Si5323, Si5326, Si5366, and Si5368 are jitter-attenuating clock multipliers that provide ultra-low jitter generation as low as 0.30 ps RMS.
  • Page 12 PLL. Silicon Laboratories offers a PC-based software utility, DSPLLsim that can be used to determine valid frequency plans and loop bandwidth settings for the Any-Rate Precision Clock product family. For the microprocessor- controlled devices, DSPLLsim provides the optimum PLL divider settings for a given input frequency/clock multiplication ratio combination that minimizes phase noise and power consumption.

  • Page 13: Si5324 Introduction

    Si53xx-RM 1.1. Si5324 Introduction The Si5324 is a low loop BW version of the Si5326. As such, all of the descriptions and documentation associated with the Si5326 that is found in the Any-Rate Precision Clocks Family Reference Manual (this document) can be applied to directly to the Si5324 with some exceptions.

  • Page 14: Narrowband Versus Wideband Overview

    Si53xx-RM 2. Narrowband Versus Wideband Overview The narrowband (NB) devices offer a number of features and capabilities that are not available with the wideband (WB) devices, as outlined in the below list: Richer set of frequency plans due to more divisor options ...

  • Page 15: Any-Rate Clock Family Members

    Si53xx-RM 3. Any-Rate Clock Family Members 3.1. Si5316 The Si5316 is a low jitter, precision jitter attenuator for high-speed communication systems, including OC-48, OC- 192, 10G Ethernet, and 10G Fibre Channel. The Si5316 accepts dual clock inputs in the 19, 38, 77, 155, 311, or 622 MHz frequency range and generates a jitter-attenuated clock output at the same frequency.

  • Page 16: Si5319

    The Si5319 input clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface. The Si5319 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides any-rate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components.

  • Page 17: Si5322

    Si53xx-RM 3.3. Si5322 The Si5322 is a low jitter, precision clock multiplier for high-speed communication systems, including SONET OC- 48/OC-192, Ethernet, and Fibre Channel. The Si5322 accepts dual clock inputs ranging from 19.44 to 707 MHz and generates two frequency-multiplied clock outputs ranging from 19.44 to 1050 MHz. The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, Fibre Channel rates, and broadcast video.

  • Page 18: Si5323

    Si53xx-RM 3.4. Si5323 The Si5323 is a jitter-attenuating precision clock multiplier for high-speed communication systems, including SONET OC-48/OC-192, Ethernet, and Fibre Channel. The Si5323 accepts dual clock inputs ranging from 8 kHz to 707 MHz and generates two frequency-multiplied clock outputs ranging from 8 kHz to 1050 MHz. The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, Fibre Channel, and broadcast video rates.

  • Page 19: Si5325

    Si53xx-RM 3.5. Si5325 The Si5325 is a low jitter, precision clock multiplier for applications requiring clock multiplication without jitter attenuation. The Si5325 accepts dual clock inputs ranging from 10 to 710 MHz and generates two independent, synchronous clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device provides virtually any frequency translation combination across this operating range.

  • Page 20: Si5326

    Si53xx-RM 3.6. Si5326 The Si5326 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance. The Si5326 accepts dual clock inputs ranging from 2 kHz to 710 MHz and generates two independent, synchronous clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device provides virtually any frequency translation combination across this operating range.

  • Page 21: Si5365

    Si53xx-RM 3.7. Si5365 The Si5365 is a low jitter, precision clock multiplier for high-speed communication systems, including SONET OC- 48/OC-192, Ethernet, and Fibre Channel, in which the application requires clock multiplication without jitter attenuation. The Si5365 accepts four clock inputs ranging from 19.44 MHz to 707 MHz and generates five frequency-multiplied clock outputs ranging from 19.44 MHz to 1050 MHz.

  • Page 22: Si5366

    Si53xx-RM 3.8. Si5366 The Si5366 is a jitter-attenuating precision clock multiplier for high-speed communication systems, including SONET OC-48/OC-192, Ethernet, and Fibre Channel. The Si5366 accepts four clock inputs ranging from 8 kHz to 707 MHz and generates five frequency-multiplied clock outputs ranging from 8 kHz to 1050 MHz. The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, and Fibre Channel rates.

  • Page 23: Si5367

    Si53xx-RM 3.9. Si5367 The Si5367 is a low jitter, precision clock multiplier for applications requiring clock multiplication without jitter attenuation. The Si5367 accepts four clock inputs ranging from 10 to 707 MHz and generates five frequency- multiplied clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device provides virtually any frequency translation combination across this operating range.

  • Page 24: Si5368

    Si53xx-RM 3.10. Si5368 The Si5368 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps rms jitter performance. The Si5368 accepts four clock inputs ranging from 2 kHz to 710 MHz and generates five independent, synchronous clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device provides virtually any frequency translation combination across this operating range.

  • Page 25: Specifications

    Si53xx-RM 4. Specifications Table 2. Recommended Operating Conditions Parameter Symbol Test Condition Min Typ Max Unit           Ambient Temperature –40 25 ºC Note Note Note Note      ...
  • Page 26 Si53xx-RM Table 3. DC Characteristics—All Parts (Current draw is independent of supply voltage) Parameter Symbol Test Condition Typ Max Units   Supply Current LVPECL Format — 622.08 MHz Out     — All CKOUT’s Enabled     —...
  • Page 27 Si53xx-RM Table 3. DC Characteristics—All Parts (Current draw is independent of supply voltage) (Continued) Parameter Symbol Test Condition Typ Max Units Output Clocks (CKOUTn—See “8.2. Output Clock Drivers” for Configuring Output Drivers for LVPECL/CML/LVDS/CMOS)           LVPECL 100 ...
  • Page 28 Si53xx-RM Table 3. DC Characteristics—All Parts (Current draw is independent of supply voltage) (Continued) Parameter Symbol Test Condition Typ Max Units       Output Short to = 3.63 V — ISC+ CML, LVDS, LVPECL           = 1.89 V —...
  • Page 29 Si53xx-RM Table 3. DC Characteristics—All Parts (Current draw is independent of supply voltage) (Continued) Parameter Symbol Test Condition Typ Max Units Output Drive CMOS Current Driving into CKO for output low or CKO- for output high. CKOUT+ and CKOUT– shorted externally.
  • Page 30 Si53xx-RM Table 3. DC Characteristics—All Parts (Current draw is independent of supply voltage) (Continued) Parameter Symbol Test Condition Typ Max Units           Weak Internal 24.6 — k Input Pulldown Resistor 3-Level Input Pins ...
  • Page 31 Si53xx-RM Table 4. DC Characteristics—Microprocessor Devices (Si5319, Si5325, Si5326, Si5367, Si5368) Parameter Symbol Test Condition Units C Bus Lines (SDA, SCL)      Input Voltage Low — — 0.25 x V ILI2C      Input Voltage High 0.7 x V —...
  • Page 32 Si53xx-RM CLKOUT_2 FSYNC CLKIN_4* FSSU FSYNC_ALIGN LATF LATF FSYNCOUT* * CLKIN_2 and CLKIN_4 are the active input clock and frame sync pair in this example Figure 13. Frame Synchronization Timing in Level Sensitive Mode CLKOUT_2 FSYNC CLKIN_4* FSSU FSYNC_ALIGN LATF FSYNCOUT* Fixed number of CLKOUT_2 clock cycles.
  • Page 33 Si53xx-RM Table 6. AC Characteristics—All Parts Parameter Symbol Test Condition Units  Input Frequency 19.38 —   19.43 — 707.35      0.002 — 707.35   —  — 0.008 — When used as frame synchronization input ...
  • Page 34 Si53xx-RM Table 6. AC Characteristics—All Parts (Continued) Parameter Symbol Test Condition Units LVCMOS Pins           Input Capacitance — —         INC/DEC Pulse — — µs Width ...
  • Page 35 Si53xx-RM Table 6. AC Characteristics—All Parts (Continued) Parameter Symbol Test Condition Units      From last XA clock  LOSX Trigger LOSX- — Window to internal detection TRIG of LOSX      Time to Clear LOS Measured from —...
  • Page 36 Si53xx-RM Table 6. AC Characteristics—All Parts (Continued) Parameter Symbol Test Condition Units       FOS Trigger FOS_THR[1:0] = 10 — ±ppm Threshold (SMC Clock w/Stra- (Frequency offset at which FOS is 3/3E reference) declared)       FOS_THR[1:0] = 01 —...
  • Page 37 Si53xx-RM Table 6. AC Characteristics—All Parts (Continued) Parameter Symbol Test Condition Units     Time to Clear FOS Measured from — Alarm appearance of valid CKIN to of FOS alarm VALTIME[1:0] = 00,     Measured from —...
  • Page 38 Si53xx-RM Table 6. AC Characteristics—All Parts (Continued) Parameter Symbol Test Condition Units Device Skew     of CKOUT_n to of Output Clock — — SKEW Skew, CKOUT_m, see Section 7.7.4 CKOUT_n and CKOUT_m at same frequency and signal format ...
  • Page 39 Si53xx-RM Table 6. AC Characteristics—All Parts (Continued) Parameter Symbol Test Condition Units   FSYNC Phase — — PHLSBF Adjust Resolution CKOUT2   FS_OUT Phase Usable settings lim- — — 131,071 PHRNGF Adjust Range ited to less than 1 period of FS_OUT PHLSBF PLL Performance...
  • Page 40 Si53xx-RM Table 6. AC Characteristics—All Parts (Continued) Parameter Symbol Test Condition Units     Output Clock Initial During clock switch — Phase Step f3 > 128 kHz     f3 < 128 kHz — — P_STEP ...
  • Page 41 Si53xx-RM Table 7. Jitter Generation (Si5316, Si5319, Si5323, Si5326, Si5366, Si5368) Parameter Symbol GR-253 Spec Unit 1,2,3,4,5 Test Condition Measurement DSPLL BW Filter (MHz) 0.02–80 120 Hz — 30 ps pp/0.3 UIpp — .378 7.85 kHz — 30 ps pp/0.3 UIpp —...
  • Page 42 Si53xx-RM Table 8. Jitter Generation (Si5322, Si5325, Si5365, Si5367) Parameter Symbol Unit Test Condition Measurement DSPLL BW Filter (MHz) (kHz) Jitter Gen OC-192 0.02–80 1096 — — .400 4–80 1096 — — .190 0.05–80 1096 — — .390 Jitter Gen OC-48 0.012–20 1096 —...
  • Page 43 Si53xx-RM SCLK Figure 15. SPI Timing Diagram Table 10. Thermal Characteristics Parameter Symbol Test Condition Devices Value Unit  Thermal Resistance Junction to Ambient Still Air Si5316, Si5319, ºC/W Si5322, Si5323, Si5325, Si5326 Si5365, Si5366, ºC/W Si5367, Si5368 Rev. 0.41...

  • Page 44: Dspll (All Devices)

    Si53xx-RM 5. DSPLL (All Devices) All members of the Any-Rate Precision Clocks family incorporate a phase-locked loop (PLL) that utilizes Silicon Laboratories' third generation DSPLL technology to eliminate jitter, noise, and the need for external VCXO and loop filter components found in discrete PLL implementations. This is achieved by using a digital signal processing (DSP) algorithm to replace the loop filter commonly found in discrete PLL designs.

  • Page 45: Pll Performance

    To assist users in finding valid divider settings for a particular input frequency and clock multiplication ratio, Silicon Laboratories offers PC-based software (DSPLLsim) that calculates these settings automatically. When multiple divider combinations produce the same output frequency, the software recommends the divider settings yielding the recommended settings for phase noise performance and power consumption.

  • Page 46: Jitter Tolerance

    Si53xx-RM 5.2. PLL Performance All members of the Any-Rate Precision Clock family of devices provide extremely low jitter generation, a well- controlled jitter transfer function, and high jitter tolerance. 5.2.1. Jitter Generation Jitter generation is defined as the amount of jitter produced at the output of the device with a jitter free input clock. Generated jitter arises from sources within the VCO and other PLL components.

  • Page 47: Pin Control Parts (Si5316, Si5322, Si5323, Si5365, Si5366)

    Si53xx-RM 5.2.3. Jitter Tolerance Jitter tolerance is defined as the maximum peak-to-peak sinusoidal jitter that can be present on the incoming clock before the DSPLL loses lock. The tolerance is a function of the jitter frequency, because tolerance improves for lower input jitter frequency.
  • Page 48 Si53xx-RM 6. Pin Control Parts (Si5316, Si5322, Si5323, Si5365, Si5366) These parts provide high-performance clock multiplication with simple pin control. Many of the control inputs are three levels: High, Low, and Medium. High and Low are standard voltage levels determined by the supply voltage: and Ground.

  • Page 49: Clock Multiplication (Si5322, Si5323, Si5365, Si5366)

    Si53xx-RM The Si5316 can accept a CKIN1 input at a different frequency than the CKIN2 input. The frequency of one input clock can be 1x, 4x, or 32x the frequency of the other input clock. The output frequency is always equal to the lower of the two clock inputs and is set via the FRQSEL [1:0] pins.
  • Page 50 Si53xx-RM 6.1.2. Clock Multiplication (Si5322, Si5323, Si5365, Si5366) These parts provide flexible frequency plans for SONET, DATACOM, and interworking between the two (Table 15, Table 16, and Table 17 respectively). For these parts, all of the CKINn inputs must be the same frequency as specified in the tables.
  • Page 51 Si53xx-RM Table 15. SONET Clock Multiplication Settings (FRQTBL=L) (Continued) FRQSEL (MHz) Mult Factor Nominal All Devices Si5366 Only [3:0] * (MHz) (MHz) FS_OUT (MHz) CKOUT5 (CK_CONF = 1) (CK_CONF = 0)  LLHM 19.44 19.44 19.44 0.008  LLHH 38.88 38.88 0.008 ...
  • Page 52 Si53xx-RM Table 15. SONET Clock Multiplication Settings (FRQTBL=L) (Continued) FRQSEL (MHz) Mult Factor Nominal All Devices Si5366 Only [3:0] * (MHz) (MHz) FS_OUT (MHz) CKOUT5 (CK_CONF = 1) (CK_CONF = 0)  MLLM 77.76 19.44 19.44 0.008  MLLH 38.88 38.88 0.008 ...
  • Page 53 Si53xx-RM Table 15. SONET Clock Multiplication Settings (FRQTBL=L) (Continued) FRQSEL (MHz) Mult Factor Nominal All Devices Si5366 Only [3:0] * (MHz) (MHz) FS_OUT (MHz) CKOUT5 (CK_CONF = 1) (CK_CONF = 0) HLLL 167.33 237/255 155.52 155.52  MMHM 167.33 167.33 HLLM 4 x (237/255) 622.08...
  • Page 54 Si53xx-RM Table 15. SONET Clock Multiplication Settings (FRQTBL=L) (Continued) FRQSEL (MHz) Mult Factor Nominal All Devices Si5366 Only [3:0] * (MHz) (MHz) FS_OUT (MHz) CKOUT5 (CK_CONF = 1) (CK_CONF = 0) HHLH 669.33 1/4 x 237/255 155.52 155.52  HMML 167.33 167.33 HHML...
  • Page 55 Si53xx-RM Table 16. Datacom Clock Multiplication Settings (FRQTBL = M, CK_CONF=0) Setting FRQSEL[3:0] (MHz) Mult Factor * (MHz)  LLLL 15.625 31.25  LLLM 62.5  LLLH  LLML  LLMM 17/4 106.25  LLMH LLHL 25/4 x 66/64 161.13 LLHM 51/8 x 66/64 164.36...
  • Page 56 Si53xx-RM Table 16. Datacom Clock Multiplication Settings (FRQTBL = M, CK_CONF=0) (Continued) Setting FRQSEL[3:0] (MHz) Mult Factor * (MHz)  MLHM 10/8 x 66/64 161.13 MLHH 10/8 x 66/64 x 255/238 172.64 MMLL 10/8 x 66/64 x 255/237 173.37  MMLM 5 x 66/64 644.53...
  • Page 57 Si53xx-RM Table 16. Datacom Clock Multiplication Settings (FRQTBL = M, CK_CONF=0) (Continued) Setting FRQSEL[3:0] (MHz) Mult Factor * (MHz) HLML 173.37 4/5 x 64/66 x 237/255 HLMM 64/66 x 237/255 156.25  HLMH 237/255 161.13 HLHL 4 x 237/255 644.53 ...
  • Page 58 Si53xx-RM Table 16. Datacom Clock Multiplication Settings (FRQTBL = M, CK_CONF=0) (Continued) Setting FRQSEL[3:0] (MHz) Mult Factor * (MHz) HHML 693.48 1/5 x 64/66 x 237/255 HHMM 1/4 x 64/66 x 237/255 156.25  HHMH 1/4 x 237/255 161.13  HMML 173.37 HHHL...
  • Page 59 Si53xx-RM Table 17. SONET to Datacom Clock Multiplication Settings Setting FRQSEL[3:0] (MHz) Mult Factor * (MHz) LLLL 0.008 3125 LLLM 6480 51.84 LLLH 53125/8 53.125 LLML 15625/2 62.5 LLMM 53125/4 106.25 LLMH 15625 LLHL 78125/4 156.25 LLHM 159375/8 159.375 LLHH 53125/2 212.5 LMLL...
  • Page 60 Si53xx-RM Table 17. SONET to Datacom Clock Multiplication Settings (Continued) Setting FRQSEL[3:0] (MHz) Mult Factor * (MHz)  MLML 62.500  MLMM MLMH 74.176 91/250 MLHL 74.17582 MLHM 91 x 11/250 x 4 74.25 MLHH 74.250 4/11 MMLL 4 x 250/11 x 91 74.17582 MMLM 74.25...

  • Page 61: Ckout3 And Ckout4 (Si5365 And Si5366)

    Si53xx-RM Table 17. SONET to Datacom Clock Multiplication Settings (Continued) Setting FRQSEL[3:0] (MHz) Mult Factor * (MHz) MHHM 155.520 15625/15552 156.25 MHHH 31875/31104 159.375 HLLL 15625/15552 x 66/64 161.13 HLLM 31875/31104 x 66/64 164.36 HLLH 15625/15552 x 66/ 172.64 64 x 255/238 HLML 31875/31104 x 66/ 176.1...

  • Page 62: Wideband Performance (Si5322 And Si5365)

    Si53xx-RM 6.1.3. CKOUT3 and CKOUT4 (Si5365 and Si5366) Submultiples of the output frequency on CKOUT1 and CKOUT2 can be produced on the CKOUT3 and CKOUT4 outputs using the DIV34 [1:0] control pins as shown in Table 18. Table 18. Clock Output Divider Control (DIV34) DIV34[1:0] Output Divider Value 6.1.4.
  • Page 63 Si53xx-RM 6.1.7. Wideband Performance (Si5322 and Si5365) These devices operate as wideband clock multipliers without an external resonator or reference clock. They are ideal for applications where the input clock is already low jitter and only simple clock multiplication is required. A limited selection of clock multiplication factors is available (See Table 15, Table 16, and Table 17).

  • Page 64: Pin Control Input Clock Control

    Si53xx-RM Table 19. Si5316, Si5322, and Si5323 Pins and Reset Pin # Si5316 Pin Si5322 Pin Si5323 Pin Must Reset after Changing Name Name Name FRQTBL FRQTBL RATE 0 RATE 0 DBL_BY DBL2_BY DBL2_BY RATE1 RATE1 BWSEL0 BWSEL0 BWSEL0 BWSEL1 BWSEL1 BWSEL1 FRQSEL0...

  • Page 65: Automatic Clock Selection (Si5322, Si5323, Si5365, Si5366)

    Si53xx-RM Table 20. Si5365 and Si5366 Pins and Reset Pin # Si5365 Pin Name Si5366 Pin Name Must Reset after Changing SFOUT1 No, but skew not guaranteed without Reset SFOUT0 No, but skew not guaranteed without Reset 6.3. Pin Control Input Clock Control This section describes the clock selection capabilities (manual input selection, automatic input selection, hitless switching, and revertive switching).

  • Page 66: Hitless Switching With Phase Build-Out (Si5323, Si5366)

    Si53xx-RM 6.3.2. Automatic Clock Selection (Si5322, Si5323, Si5365, Si5366) The AUTOSEL input pin sets the input clock selection mode as shown in Table 23. Automatic switching is either revertive or non-revertive. Setting AUTOSEL to M or H, changes the CSn_CAm pins to output pins that indicate the state of the automatic clock selection (See Table 24 and Table 25).

  • Page 67: Digital Hold/Vco Freeze

    CKINn that becomes valid. 6.3.3. Hitless Switching with Phase Build-Out (Si5323, Si5366) Silicon Laboratories switching technology performs "phase build-out" to minimize the propagation of phase transients to the clock outputs during input clock switching. All switching between input clocks occurs within the input multiplexor and phase detector circuitry.
  • Page 68 Si53xx-RM 6.4. Digital Hold/VCO Freeze All Any-Rate Precision Clock devices feature a hold over or VCO freeze mode, whereby the DSPLL is locked to a digital value. 6.4.1. Narrowband Digital Hold (Si5316, Si5323, Si5366) If an LOS or FOS condition exists on the selected input clock, the device enters digital hold. In this mode, the device provides a stable output frequency until the input clock returns and is validated.
  • Page 69 Si53xx-RM 6.6. Output Phase Adjust (Si5323, Si5366) Overall device skew (CKINn to CKOUT_n phase delay) is controllable via the INC and DEC input pins. A positive pulse applied at the INC pin increases the device skew by 1/f , one period of the DCO output clock. A pulse on the DEC pin decreases the skew by the same amount.
  • Page 70 Si53xx-RM 6.6.5. Disabling FS_OUT (Si5366) The FS_OUT maybe disabled via the DBLFS pin, see Table 28. The additional state (M) provided allows for FS_OUT to drive a CMOS load while the other clock outputs use a different signal format as specified by the SFOUT[1:0] pins.
  • Page 71 Si53xx-RM 6.8. PLL Bypass Mode The Device supports a PLL Bypass Mode in which the selected input clock is fed directly to all enabled output buffers, bypassing the DSPLL. In PLL Bypass Mode, the input and output clocks will be at the same frequency. PLL Bypass Mode is useful in a laboratory environment to measure system performance with and without the jitter attenuation provided by the DSPLL.
  • Page 72 Si53xx-RM Table 31. Frequency Offset Control (FOS_CTL) FOS_CNTL Meaning FOS Disabled. Stratum 3/3E FOS Threshold (12 ppm) SONET Minimum Clock Threshold (48 ppm) 6.9.3. FSYNC Align Alarm (Si5366 and CK_CONF = 1 and FRQTBL = L) At power-up or any time after the PLL has lost lock and relocked, the device automatically performs a realignment of FS_OUT using the currently active sync input.
  • Page 73 PLL Self-Calibration (See “6.2. PLL Self-Calibration”). 6.11. DSPLLsim Configuration Software To simplify frequency planning, loop bandwidth selection, and general device configuration of the Any-Rate Precision Clocks. Silicon Laboratories has a configuration utility-DSPLLsim. This software is available to download from http://www.silabs.com/timing. Rev. 0.41...
  • Page 74 To assist users in finding valid divider settings for a particular input frequency and clock multiplication ratio, Silicon Laboratories offers PC-based software (DSPLLsim) that calculates these settings automatically. When multiple divider combinations produce the same output frequency, the software recommends the divider settings that yield the best combination of phase noise performance and power consumption.
  • Page 75 Si53xx-RM 7.1.2. Wideband Mode (Si5325, Si5367) These devices operate as wideband clock multipliers without an external resonator or reference clock. This mode may be desirable if the input clock is already low jitter and only simple clock multiplication is required. A limited selection of clock multiplication factors is available in this mode.
  • Page 76 Note: For some input frequency/clock multiplication ratio combinations, multiple divider settings produce the same output frequency. Divider settings listed above are based on Silicon Laboratories’ DSPLLsim software that estimates which divider setting produces the best phase noise performance while minimizing power consumption.
  • Page 77 Note: Loop bandwidth is a function of phase detector frequency f3. For some input frequency/clock multiplication ratio combinations, multiple divider settings produce the same output frequency. Loop bandwidth settings listed above are based on Silicon Laboratories’ DSPLLsim software that estimates which divider setting produces the best phase noise performance while minimizing power consumption.
  • Page 78 Si53xx-RM 7.1.3. Narrowband Mode (Si5319, Si5326, Si5368) The DCO uses the reference clock on the XA/XB pins as its reference for jitter attenuation. The XA/XB pins support either a crystal oscillator or an input buffer (single-ended or differential) so that an external oscillator can become the reference source.
  • Page 79 Si53xx-RM Table 38. Narrowband Frequency Limits Signal Frequency Limits CKINn 2 kHz–710 MHz 2 kHz–2 MHz 4.85–5.67 GHz 2 kHz–1.475 GHz Table 39. Dividers and Limits Divider Equation Si5325, Si5367 Si5319, Si5326, Si5368 N1 = N1_HS x NCn_LS N1_HS = [4, 5, …, 11] N1_HS = [4, 5, …, 11] NCn_LS = [1, 2, 4, 6, …, 2^20] NCn_LS = [1, 2, 4, 6, …, 2^20]...
  • Page 80 Note: For some input frequency/clock multiplication ratio combinations, multiple divider settings produce the same output frequency. Divider settings listed above are based on Silicon Laboratories’ DSPLLsim software that estimates which divider setting produces the best phase noise performance while minimizing power consumption. See the Register Map documentation for the appropriate write values.
  • Page 81 Loop bandwidth settings listed above are based on Silicon Laboratories’ DSPLLsim software that estimates which divider setting produces the best phase noise performance while minimizing power consumption.
  • Page 82 Si53xx-RM 7.2. PLL Self-Calibration The device performs an internal self-calibration before operation to optimize loop parameters and jitter performance. While the self-calibration is being performed, the DCO is being internally controlled by the self- calibration state machine, and the LOL alarm will be active. The output clocks can either be active or disabled depending on the SQ_ICAL bit setting.
  • Page 83 Si53xx-RM 7.3. Input Clock Configurations (Si5367 and Si5368) The device supports two input clock configurations based on the CK_CONFIG_REG register bit as shown in Table 42: Table 42. Input Clock Configurations CK_CONFIG_REG Input Clock Configuration CKIN1,2,3,4 Inputs No FS_OUT Alignment CKIN1,3 &...
  • Page 84 Si53xx-RM CKIN1 CKIN1 CKIN2 CKIN2 Selected Selected Clock Clock CKIN3 CKIN3 CKIN4 CKIN4 LOS/FOS LOS/FOS LOS/FOS LOS/FOS LOS/FOS LOS/FOS LOS/FOS LOS/FOS LOS/FOS LOS/FOS LOS/FOS LOS/FOS detect detect detect detect detect detect detect detect detect detect detect detect CK_PRIORn CK_PRIORn Clock priority logic Clock priority logic CS0_C3A, CS0_C3A,...
  • Page 85 Si53xx-RM 7.4.1. Manual Clock Selection Manual control of input clock selection is available by setting the AUTOSEL_REG[1:0] register bits to 00. In manual mode, the active input clock is chosen via the CKSEL_REG[1:0] register setting according to Table 43 and Table 44.
  • Page 86 Si53xx-RM 7.4.2.1. Detailed Automatic Clock Selection Description (Si5325, Si5326) Automatic switching is either revertive or non-revertive. The default prioritization of clock inputs when the device is configured for automatic switching operation is CKIN1, followed by CKIN2, and finally, digital hold mode. The inverse input clock priority arrangement is available through the CK_PRIOR bits, as shown in the Si5325 and Si5326 Register Maps.
  • Page 87 7.4.3. Hitless Switching with Phase Build-Out (Si5326, Si5368) Silicon Laboratories switching technology performs phase build-out, which maintains the phase of the output when the input clock is switched. This minimizes the propagation of phase transients to the clock outputs during input clock switching.
  • Page 88 Si53xx-RM 7.5. Si5319, Si5326, and Si5368 Free Run Mode Si5319, Crystal or an external oscillator Si5326, Si5368 Xtal osc XA-XB   CKIN1 DSPLL CKOUT1   CKOUT2 Core CKIN2 Control C/SPI Figure 25. Free Run Mode Block Diagram CKIN2 has an extra mux with a path to the crystal oscillator output. ...
  • Page 89 Si53xx-RM 7.5.3. Free Run Reference Frequency Constraints XA-XB freq, XA-XB freq, max Xtal 163 MHz 180 MHz 3rd overtone 109 MHz 125.5 MHz 3rd overtone 55 MHz 61 MHz 3rd overtone 37 MHz 41 MHz fundamental CKIN XA-XB -------------- - ----------------- - CKOUT ...
  • Page 90 Si53xx-RM 7.6. Digital Hold All Any-Rate Precision Clock devices feature a holdover mode, whereby the DSPLL is locked to a digital value. 7.6.1. Narrowband Digital Hold (Si5316, Si5326, Si5368) After the part's initial self-calibration (ICAL), when no valid input clock is available, the device enters digital hold. Referring to the logical diagram in "Appendix D—Alarm Structure"...
  • Page 91 Si53xx-RM Table 47. Digital Hold History Delay (Continued) HIST_DEL[4:0] History Delay Time (ms) HIST_DEL[4:0] History Delay Time (ms) 01000 0.03 11000 1678 01001 0.05 11001 3355 01010 0.10 11010 6711 01011 0.20 11011 13422 01100 0.41 11100 26844 01101 0.82 11101 53687 01110...
  • Page 92 Si53xx-RM 7.6.3. VCO Freeze (Si5319, Si5325, Si5367) If an LOS or FOS condition exists on the selected input clock, the device enters VCO freeze. In this mode, the device provides a stable output frequency until the input clock returns and is validated. When the device enters digital hold, the internal oscillator is initially held to its last frequency value.
  • Page 93 5 GHz and N1_HS = (4, 5, 6, …, 11), the resolution varies from approximately 800 ps to 2.2 ns depending on the PLL divider settings. Silicon Laboratories' PC-based configuration software (DSPLLsim) provides PLL divider settings for each frequency translation, if applicable. If more than one set of PLL divider settings is available, selecting the combination with the lowest N1_HS value provides the finest resolution for output clock phase offset control.
  • Page 94 Si53xx-RM Table 49. CKIN3/CKIN4 Frequency Selection (CK_CONF = 1) CKLNnRATE[2:0] CKINn Frequency (kHz) Divisor 2–4 4–8 8–16 16–32 32–64 64–128 128–256 256–512 DCO, DCO,     N1_HS N1_HS CKOUT2 4.85 GHz 4.85 GHz NC2_LS NC2_LS to 5.67 GHz to 5.67 GHz ...
  • Page 95 Si53xx-RM The NC5_LS divider uses CKOUT2 as its clock input to derive FS_OUT. The limits for the NC5_LS divider are NC5_LS = [1, 2, 4, 6, …, 2 < 710 MHz CKOUT2 Note that when in frame synchronization realignment mode, writes to NC5_LS are controlled by FPW_VALID. See section “7.8.4.
  • Page 96 Si53xx-RM phase relationship, a realignment can be performed. A realignment request may cause FS_OUT to instantaneously shift its output edge location in order to align with the active input sync phase. Table 51. Alignment Alarm Trigger Threshold ALIGN_THR [2:0] Alarm Trigger Threshold (Units of T CKOUT2 For cases where phase skew is required, see Section “7.7.
  • Page 97 Si53xx-RM 7.8.4. FS_OUT Polarity and Pulse Width Control (Si5368) Additional output controls are available for FS_OUT. The active polarity of FS_OUT is set via the FS_OUT_POL register bit and the active duty cycle is set via the FSYNC_PW[9:0] register. Pulse width settings have a resolution of 1/f , and a 50% duty cycle setting is provided.
  • Page 98 Si53xx-RM 7.9. Output Clock Drivers (Si5319, Si5325, Si5326, Si5367, Si5368) The device includes a flexible output driver structure that can drive a variety of loads, including LVPECL, LVDS, CML, and CMOS formats. The signal format of each output is individually configurable through the SFOUTn_REG[2:0] register bits, which modify the output common mode and differential signal swing.
  • Page 99 Si53xx-RM 7.11. Alarms (Si5319, Si5325, Si5326, Si5367, Si5368) Summary alarms are available to indicate the overall status of the input signals and frame alignment (Si5368 only). Alarm outputs stay high until all the alarm conditions for that alarm output are cleared. The Register VALTIME controls how long a valid signal is re-applied before an alarm clears.
  • Page 100 Si53xx-RM 7.11.1.3. LOSA (Si5319, Si5326, Si5368) A slower response version of LOS called LOSA is available and should be used under certain conditions. Because LOSA is slower and less sensitive than LOS, its use should be considered for applications with quasi-periodic clocks (e.g., gapped clocks with one or more consecutive clock edges removed), when switching between input clocks with a large difference in frequency and any other application where false positive assertions of LOS may incorrectly cause the Any-Rate device to be forced into Digital Hold.
  • Page 101 Si53xx-RM Table 55. FOS Reference Clock Selection FOS Reference FOSREFSEL[2:0] Si5326 Si5368 XA/XB XA/XB CKIN1 CKIN1 CKIN2 (default) CKIN2 (default) Reserved CKIN3 Reserved CKIN4 all others Reserved Reserved Both the FOS reference and the FOS monitored clock must be divided down to the same clock rate and this clock rate must be between 10 MHz and 27 MHz.
  • Page 102 Si53xx-RM 7.11.3. C1B, C2B (Si5319, Si5325, Si5326) A LOS condition causes the associated LOS1_INT or LOS2_INT read only register bit to be set. A LOS condition on CKIN_1 will also be reflected onto C1B if CK1_BAD_PIN = 1. Likewise, a LOS condition on CKIN_2 will also be reflected onto C2B if CK2_BAD_PIN = 1.
  • Page 103 Si53xx-RM 7.11.5. C1B, C2B, C3B, ALRMOUT (Si5368 [CK_CONFIG_REG = 1]) The generation of alarms on the C1B, C2B, C3B, and ALRMOUT outputs is a function of the input clock configuration, and the frequency offset alarm enable as shown in Table 58. The LOSn_INT and FOSn_INT signals are the raw outputs of the alarm monitors.
  • Page 104 Si53xx-RM Table 59. Lock Detect Retrigger Time (LOCKT) LOCKT[2:0] Retrigger Time (ms) 26.5 13.3 6.6 (value after reset) 1.66 .833 7.11.8. Device Interrupts Alarms on internal real-time status bits such as LOS1_INT, FOS1_INT, etc. cause their associated interrupt flags (LOS1_FLG, FOS1_FLG, etc.) to be set and held. The interrupt flag bits can be individually masked or unmasked with respect to the output interrupt pin.
  • Page 105 Si53xx-RM Byte Byte Slave Address Slave Address Data Data Data Data Address Address Write Command Byte Byte Slave Address Slave Address Slave Address Slave Address Data Data Data Data Address Address Read Command –address auto incremented after each data read or write (this can be two separate transactions) A –...
  • Page 106 Si53xx-RM 7.14. Serial Microprocessor Interface (SPI) When configured in SPI control mode (CMODE = H), the control interface to the device is a 4-wire interface modeled after commonly available microcontroller and serial peripheral devices. The interface consists of a clock input (SCLK), slave select input (SSb), serial data input (SDI), and serial data output (SDO).
  • Page 107 See the Register File Help File for a full description of the registers. 7.16. DSPLLsim Configuration Software To simplify frequency planning, loop bandwidth selection, and general device configuration, of the Any-Rate Precision Clocks. Silicon Laboratories has a configuration utility - DSPLLsim. This software is available to download from http://www.silabs.com/timing. Rev. 0.41...
  • Page 108 Si53xx-RM 8. High-Speed I/O 8.1. Input Clock Buffers Any-Rate Precision Clock devices provide differential inputs for the CKINn clock inputs. These inputs are internally biased to a common mode voltage [see Table 3, “DC Characteristics—All Parts (Current draw is independent of supply voltage)”] and can be driven by either a single-ended or differential source.
  • Page 109 Si53xx-RM Si53xx CKIN +  40 k CML/   LVDS Driver ± 40 k CKIN Figure 34. CML/LVDS Termination (1.8, 2.5, 3.3 V) Si53xx 39  CMOS CKIN + Driver  40 k  ± 40 k  CKIN 0.1 uF Figure 35.
  • Page 110 Si53xx-RM 8.2. Output Clock Drivers The output clocks can be configured to be compatible with LVPECL, CML, LVDS, or CMOS as shown in Table 61. Unused outputs can be left unconnected. For microprocessor-controlled devices, it is recommended to write “sleep” to SFOUTn to disable the output buffer and reduce power. Table 61.
  • Page 111 Si53xx-RM Unused output drivers should be powered down, per Table 62, or left floating. The pin-controlled parts have a DBL2_BY pin that can be used to disable CKOUT2. 3.3 V Si53xx    40 k  LVPECL Driver ± 40 k...
  • Page 112 Si53xx-RM 8.3. Crystal/Reference Clock Interfaces (Si5316, Si5319, Si5323, Si5326, Si5366, & Si5368) The device can use and external crystal or external clock as a reference. If an external clock is used, it must be ac coupled. With appropriate buffers, the same external reference clock can be applied to CKINn. Although the reference clock input can be driven single ended (See Figure 40), best performance is with a crystal or differential LVPECL source.
  • Page 113 Si53xx-RM Si53xx 1.2 V 0.01 F  LVPECL, CML, etc. 10 k 10 k 0.01 F 0.6 V Figure 42. Differential External Reference Input Example Rev. 0.41...
  • Page 114 Si53xx-RM 8.4. Three-Level (3L) Input Pins (No External Resistors) Si53xx 75 k 75 k External Driver Figure 43. Three Level Input Pins Parameter Symbol Input Voltage Low Vill — .15 x V Input Voltage Mid Vimm .45 x Vdd .55 x V Input Voltage High Vihh .85 x Vdd...
  • Page 115 Si53xx-RM 8.5. Three-Level (3L) Input Pins (With External Resistors) Si53xx 18 k 75 k 18 k 75 k External Driver One of eight resistors from a Panasonic EXB-D10C183J (or similar) resistor pack Figure 44. Three Level Input Pins Parameter Symbol Input Low Current Iill –30 µA...
  • Page 116 Si53xx-RM 9. Power Supply These devices incorporate an on-chip voltage regulator to power the device from supply voltages of 1.8, 2.5, or 3.3 V. Internal core circuitry is driven from the output of this regulator while I/O circuitry uses the external supply voltage directly.
  • Page 117 Si53xx-RM 10. Packages and Ordering Guide Please refer to the data sheet for your device. Rev. 0.41...
  • Page 118 Si53xx-RM A—N PPENDIX ARROWBAND EFERENCES Resonator/External Clock Selection Table 63 shows the approved 114.285 MHz 3rd overtone crystals. Table 63. Approved Crystals Manufacturer Part Number Web Site Stability Initial Accuracy 7MA1400014 http://www.txc.com.tw 100 ppm 100 ppm Connor Winfield CS-018 http://www.conwin.com 100 ppm 100 ppm Connor Winfield...
  • Page 119 Si53xx-RM Reference Drift During Digital Hold, long-term and temperature related drift of the reference input result in a one-to-one drift of the output frequency. That is, the stability of the any-rate output is identical to the drift of the reference frequency. This means that for the most demanding applications where the drift of a crystal is not acceptable, an external temperature compensated or ovenized oscillator will be required.
  • Page 120 Si53xx-RM B—F PPENDIX REQUENCY LANS AND ITTER ERFORMANCE (Si5316, Si5319, Si5323, Si5326, Si5366, Si5368) Introduction To achieve the best jitter performance from Narrowband Any-Rate Clock devices, a few general guidelines should be observed: High f3 Value f3 is defined as the comparison frequency at the Phase Detector. It is equal to the input frequency divided by N3. DSPLLsim automatically picks the frequency plan that has the highest possible f3 value and it reports f3 for every new frequency plan that it generates.
  • Page 121 Si53xx-RM Figure 49 shows similar results and ties them to RMS jitter values. It also helps to illustrate one potential remedy for solutions with low f3. Note that 38.88 MHz x 5 = 194.4 MHz. In this case, an FPGA was used to multiply a 38.88 MHz input clock up by a factor of five to 194.4 MHz, using a feature such as the Xilinx DCM (Digital Clock Manager).
  • Page 122 Si53xx-RM Reference vs. Output Frequency Because of internal coupling, output frequencies that are an integer multiple (or close to an integer multiple) of the XA/XB reference frequency (either internal or external) should be avoided. Figure 50 illustrates this by showing a 38.88 MHz reference being used to generate both a 622.08 MHz output (which is an integer multiple of 38.88 MHz) and 696.399 MHz (which is not an integer multiple of 38.88 MHz).
  • Page 123 Si53xx-RM High Reference Frequency When selecting a reference frequency, with all other things being equal, the higher the reference frequency, the lower the output jitter. Figures 51 and 52 illustrate this. For a discussion of the available reference frequencies, see section "...
  • Page 124 Si53xx-RM 41 MHz thru 180 MHz Ext Ref, 155.52 MHz in, 622.08 MHz out -100 -120 -140 -160 1000 10000 100000 1000000 10000000 100000000 Offset Frequency (Hz) Dark Blue—41 MHz Light Blue—61 MHz Red—125.5 MHz Green—180 MHz Figure 52. Jitter vs. Reference Frequency (2 of 2) All phase noise numbers are in fs, RMS External Reference Frequency: 125.5...
  • Page 125 Si53xx-RM C—T PPENDIX YPICAL HASE OISE LOTS Introduction The following are some typical phase noise plots. The clock input source was a Rohde and Schwarz model SML03 RF Generator. The spectrum analyzer was either an Agilent model E4400A or an Agilent model JS-500. The Any- Rate part was an Si5326 operating at 3.3 V with an ac coupled differential PECL output and an ac coupled differential sine wave input from the RF generator at 0 dBm.
  • Page 126 Si53xx-RM 622.08 MHz in, 622.08 MHz out -100 -120 -140 -160 1000 10000 100000 1000000 Offset Frequency (Hz) Jitter Band Jitter, RMS SONET_OC48, 12 kHz to 20 MHz 255 fs SONET_OC192_A, 20 kHz to 80 MHz 269 fs Brick Wall, 800 Hz to 80 MHz 274 fs Rev.
  • Page 127 Si53xx-RM 38.88 MHz in, 622.08 MHz out -100 -120 -140 -160 1000 10000 100000 1000000 10000000 100000000 Offset Frequency (Hz) Dark Blue—Normal operation Light Blue—In Digital Hold Jitter Band Normal operation, Digital Hold, Dark blue Light blue SONET_OC48, 12 kHz to 20 MHz 344 fs, RMS 339 fs, RMS SONET_OC192_A, 20 kHz to 80 MHz...
  • Page 128 Si53xx-RM Wireless Base Station 61.44 MHz in, 491.52 MHz out -100 -120 -140 -160 1000 10000 100000 1000000 10000000 100000000 Offset Frequency (Hz) Jitter Band Jitter Brick Wall, 10 Hz to 100 MHz 1.78 ps, RMS 800 Hz to 100 MHz 391 fs, RMS Rev.
  • Page 129 Si53xx-RM Digital Video (HD-SDI) 27 MHz in, 148.5 MHz out -100 -120 -140 -160 1000 10000 100000 1000000 10000000 100000000 Offset Frequency (Hz) Jitter Band Jitter Brick Wall, 10 Hz to 20 MHz 2.42 ps, RMS Peak-to-peak 14.0 ps Rev. 0.41...
  • Page 130 Si53xx-RM Digital Video 74.25 MHz in, 296.7 MHz out -100 -120 -140 -160 1000 10000 100000 1000000 10000000 100000000 Offset Frequency (Hz) Jitter Band Jitter Brick Wall, 10 Hz to 20 MHz 2.32 ps, RMS Peak-to-peak 9.61 ps Rev. 0.41...
  • Page 131 Si53xx-RM Miscellaneous 10 MHz in, 1 GHz out -100 -120 -140 -160 1000 10000 100000 1000000 10000000 100000000 Offset Frequency (Hz) Jitter Band Jitter, RMS Brick Wall, 100 Hz to 100 MHz 1,938 fs SONET_OC48, 12 kHz to 20 MHz 307 fs SONET_OC192_A, 20 kHz to 80 MHz 316 fs...
  • Page 132 Si53xx-RM 19.44 MHz in, 672.16 MHz out -100 -120 -140 -160 1000 10000 100000 1000000 10000000 100000000 Offset Frequency (Hz) Jitter Band Jitter, RMS Brick Wall, 100 Hz to 10 MHz 1,072 fs SONET_OC48, 12 kHz to 20 MHz 279 fs SONET_OC192_A, 20 kHz to 80 MHz 298 fs SONET_OC192_B, 4 MHz to 80 MHz...
  • Page 133 Si53xx-RM 402.9kHz in, 624.7 MHz out -100 -120 -140 -160 1000 10000 100000 1000000 10000000 100000000 Offset Frequency (Hz) Note: In this case, f3 = 5.1 kHz Jitter Band Jitter, RMS Brick Wall, 100 Hz to 10 MHz 35.48 ps SONET_OC48, 12 kHz to 20 MHz 843 fs SONET_OC192_A, 20 kHz to 80 MHz...
  • Page 134 Si53xx-RM 194.4 MHz in, 704.4 MHz out -100 -120 -140 -160 1000 10000 100000 1000000 10000000 100000000 Offset Frequency (Hz) Jitter Band Jitter, RMS SONET_OC48, 12 kHz to 20 MHz 293 fs SONET_OC192_A, 20 kHz to 80 MHz 317 fs SONET_OC192_B, 4 MHz to 80 MHz 180 fs SONET_OC192_C, 50 kHz to 80 MHz...
  • Page 135 Si53xx-RM 25 MHz in, 533 MHz out -100 -110 -120 -130 -140 -150 -160 1000 10000 100000 1000000 10000000 100000000 Offset Frequency (Hz) Jitter Band Jitter, RMS Brick Wall, 100 Hz to 10 MHz 1,074 fs SONET_OC48, 12 kHz to 20 MHz 337 fs SONET_OC192_A, 20 kHz to 80 MHz 357 fs...
  • Page 136 Si53xx-RM 25 MHz in, 666.7 MHz out -100 -110 -120 -130 -140 -150 -160 1000 10000 100000 1000000 10000000 100000000 Offset Frequency (Hz) Jitter Band Jitter, RMS Brick Wall, 100 Hz to 10 MHz 1,170 fs SONET_OC48, 12 kHz to 20 MHz 281 fs SONET_OC192_A, 20 kHz to 80 MHz 307 fs...
  • Page 137 Si53xx-RM 25 MHz in, 1.33 GHz out -100 -110 -120 -130 -140 -150 -160 1000 10000 100000 1000000 10000000 100000000 Offset Frequency (Hz) Jitter Band Jitter, RMS Brick Wall, 100 Hz to 10 MHz 1,050 fs SONET_OC48, 12 kHz to 20 MHz 259 fs SONET_OC192_A, 20 kHz to 80 MHz 272 fs...
  • Page 138 Si53xx-RM Narrowband versus Wide Band 25 MHz in, 1.25 GHz out -100 -120 -140 -160 1000 10000 100000 1000000 10000000 100000000 Offset Frequency (Hz) Blue—110 Hz Yellow—7.61 kHz Red—542 kHz Green—175 kHz Si5326 mode Loop BW 110 Hz BW 7.61 kHz BW 175 kHz BW 542 kHz BW Jitter Band...
  • Page 139 Si53xx-RM D—A PPENDIX LARM TRUCTURE LOS_INT LOSX_FLG Sticky LOSX_MSK Write 0 to clear INT_POL LOS1_INT LOS1_FLG Sticky LOS1_MSK Write 0 to clear LOS2_INT LOS2_FLG Sticky LOS2_MSK Write 0 to clear FOS1_INT FOS1_FLG Sticky FOS1_MSK Write 0 to clear FOS2_INT FOS2_FLG Sticky FOS2_MSK Write 0...
  • Page 140 Si53xx-RM LOS_INT LOSX_FLG Sticky LOSX_MSK Write 0 to clear INT_POL LOS1_FLG LOS1_INT Sticky LOS1_MSK Write 0 to clear LOS2_FLG LOS2_INT Sticky LOS2_MSK Write 0 to clear LOS3_INT LOS3_FLG Sticky LOS3_MSK Write 0 to clear LOS4_FLG LOS4_INT Sticky LOS4_MSK Write 0 to clear FOS1_FLG FOS1_INT...
  • Page 141 Si53xx-RM LOS3_EN LOS3_INT CKIN3 Detector CK_BAD_POL PD_CK3 Detector FOS3_EN FOS_EN LOSI_EN LOS1_INT CKIN1 Detector PD_CK1 Detector FOSI_EN FOS_EN CK_CONFIG_REG FSYNC_SWTCH_REG LOS2_EN LOS4_INT LOS2_INT CKIN2 Detector PD_CK2 Detector FOS2_EN FOS_EN Figure 55. Si5368 Alarm Diagram (2 of 2) Rev. 0.41...
  • Page 142 Si53xx-RM E—I PPENDIX NTERNAL ULLUP ULLDOWN BY Table 67. Si5316 Pullup/down Pin # Si5316 Pull? RATE0 U, D DBL2_BY U, D RATE1 U, D U, D BWSEL0 U, D BWSEL1 U, D FRQSEL0 U, D FRQSEL1 U, D CK1DIV U, D CK2DIV U, D SFOUT1...
  • Page 143 Si53xx-RM Table 69. Si5323 Pullup/down Pin # Si5323 Pull? FRQTBL U, D AUTOSEL U, D RATE0 U, D DBL2_BY U, D RATE1 U, D CS_CA U, D BWSEL0 U, D BWSEL1 U, D FRQSEL0 U, D FRQSEL1 U, D FRQSEL2 U, D FRQSEL3 U, D...
  • Page 144 Si53xx-RM Table 71. Si5326 Pullup/down Pin # Si5326 pull? RATE0 U, D RATE1 U, D CS_CA U, D A2_SS CMODE U, D Table 72. Si5365 Pullup/down Pin # Si5365 Pull? FRQTBL U, D CS0_C3A AUTOSEL U, D DBL2_BY U, D DSBL5 U, D CS1_C4A...
  • Page 145 Si53xx-RM Table 73. Si5366 Pullup/down Pin # Si5366 Pull? FRQTBL U, D CS0_C3A FS_SW FS_ALIGN AUTOSEL U, D RATE0 U, D DBL2_BY U, D RATE1 U, D DBL_FS U, D CK_CONF FOS_CTL U, D CS1_C4A U, D BWSEL0 U, D BWSEL1 U, D DIV34_0...
  • Page 146 Si53xx-RM Table 74. Si5367 Pullup/down Pin # Si5367 pull? CS0_C3A CS1_C4A U, D A2_SSB CMODE U, D Table 75. Si5368 Pullup/down Pin # Si5368 Pull? CS0_C3A FS_ALIGN RATE0 U, D RATE1 U, D CS1_C4A U, D A2_SSB CMODE U, D Rev.
  • Page 147 Si53xx-RM F—T PPENDIX YPICAL ERFORMANCE This appendix is divided into the following four sections: Bypass Mode Performance  Power Supply Noise Rejection  Crosstalk  Output Format Jitter  Bypass: 622.08 MHz In, 622.08 MHz Out 622.08 M Hz in, 622.08 M Hz out -100 -110 -120...
  • Page 148 Si53xx-RM Power Supply Noise Rejection Power Supply Noise to Output Transfer Function -100 -105 1000 38.88 MHz in, 155.52 MHz out, BW = 110 Hz Rev. 0.41...
  • Page 149 Si53xx-RM Crosstalk Results: Test Conditions Jitter Band 155.52 MHz in, 155.521 MHz in, 155.521 MHz in, 155.521 MHz in, 155.521 MHz in, 622 MHz out, 622.084 MHz 622.084 MHz 622.084 MHz 622.084 MHz For reference, out, out, out, out, No crosstalk No crosstalk 155.52 MHz 155.52 MHz...
  • Page 150 Si53xx-RM Crosstalk: Phase Noise Plots 1 5 5 . 5 2 1 M H z in , 6 2 2 .0 8 4 M H z o u t -2 0 -4 0 -6 0 -8 0 - 1 0 0 - 1 2 0 - 1 4 0 - 1 6 0...
  • Page 151 Si53xx-RM Crosstalk: Detail View 155 .521 MH z i n, 622 .084 MH z ou t -100 -110 -120 -130 1000 10000 100000 O ffset F req u ency ( Hz) Dark blue — No crosstalk Light blue — With crosstalk, low bandwidth Yellow —...
  • Page 152 Si53xx-RM Crosstalk: Wideband Comparison 155 .521 M H z in , 62 2.08 4 M H z o u t -100 -120 -140 -160 -180 1000 10000 100000 1000000 10000000 100000000 O ffse t Fre qu e ncy (H z ) Dark blue —...
  • Page 153 Si53xx-RM Crosstalk: Rohde and Schwartz RF Input R ohde and S chwarz : 155.521 M H z -100 -110 -120 1000 O ffse t Fre q ue n cy (Hz) Rev. 0.41...
  • Page 154 Si53xx-RM Jitter vs. Output Format: 19.44 MHz In, 622.08 MHz Out 1 9.4 4 M H z in , 6 2 2.0 8 M H z o ut -1 00 -1 20 -1 40 -1 60 10 0 100 0 10000 1000 00 1 000 000...
  • Page 155 Si53xx-RM OCUMENT HANGE Revision 0.3 to Revision 0.4 Updated AC Specifications in Table 6, “AC  Characteristics—All Parts” Added Si5365, Si5366, Si5367, and Si5368  operation at 3.3 V Updated Section “7.8. Frame Synchronization  Realignment (Si5368 and CK_CONFIG_REG = 1)” Added input clock control diagrams in Section “7.4.
  • Page 156 Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per- sonal injury or death may occur.

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