Operating The Adpa1107-Evalz With A Pulsed Gate Voltage; Setup; Operation - Analog Devices ADPA1107-EVALZ User Manual

UG-1962

OPERATING THE ADPA1107-EVALZ WITH A PULSED GATE VOLTAGE

Remove C4, the 1 μF capacitor, to enable fast gate pulsing
and apply a negative voltage pulse to the VGG1 input of the
ADPA1107, while the voltage on the VDDxA/VDDxB pins
of the ADPA1107 is held constant.

SETUP

All power supply, ground, and control signals are applied to
the J3 and J4 headers of the ADPA1107-EVALZ. For this mode
of operation, pulse the gate voltage between −4 V (off) and
approximately −2.6 V (on) to set the quiescent current (I
approximately 350 mA. The pulse width and duty cycle must be
approximately 100 μs and 10%, respectively.

OPERATION

Take the following steps to power-up:
1. Set VDDx/VDDx-1 (Pin 6 and Pin 8 of J3, and Pin 18 and
Pin 20 of J4) to 0 V.
2. Set VG1 (Pin 20 of J3) to off (VGG1 = −4 V).
3. Set supply voltage (V ) to 28 V.
DD
4. Turn on the gate voltage pulse (VGG1 pulsing between
−4 V and approximately −2.6 V).
5. Fine tune the pulse high voltage to achieve the desired I
(nominally 350 mA) while maintaining the pulse off
voltage level at −4 V.
6. Apply the RF input signal.
Take the following steps to power-down:
1. Turn off the RF signal.
2. Turn off the pulse to VGG1 (VGG1 = −4 V).
3. Set V
DD
4. Increase the pulse to VGG1 to 0 V.
) to
DQ
DQ
Rev. 0 | Page 6 of 14
ADPA1107-EVALZ
to 0 V.
User Guide